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hynix semiconductor 8-bit single-chip microcontrollers GMS81C2112 gms81c2120 users manual june. 2001 ver 1.00
hynix semiconductor 8-bit single-chip microcontrollers GMS81C2112 gms81c2120 users manual (ver. 1.00)
version 1.00 published by mcu application team 2001 hynix semiconductor all right reserved. additional information of this manual may be served by hynix semiconductor offices in korea or distributors and rep- resentatives listed at address directory. hynix semiconductor reserves the right to make changes to any information here in at any time without notice. the information, diagrams and other data in this manual are correct and reliable; however, hynix semiconductor is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual.

table of contents 1. overview............................................1 description .........................................................1 features .............................................................1 development tools ............................................2 ordering information 2. block diagram .................................3 3. pin assignment ................................4 4. package diagram ............................6 5. pin function......................................8 6. port structures..........................10 7. electrical characteristics ....13 absolute maximum ratings .............................13 recommended operating conditions ..............13 a/d converter characteristics .........................13 dc electrical characteristics for standard pins(5v) 14 dc electrical characteristics for high-voltage pins 15 ac characteristics ...........................................16 ac characteristics ...........................................17 typical characteristics .....................................18 8. memory organization.................20 registers ..........................................................20 program memory .............................................23 data memory ...................................................26 addressing mode .............................................30 9. i/o ports ...........................................34 10. basic interval timer..................37 11. watchdog timer..........................39 12. timer/event counter ................42 8-bit timer / counter mode ..............................44 16-bit timer / counter mode ............................48 8-bit compare output (16-bit) ..........................49 8-bit capture mode ......................................... 49 16-bit capture mode ....................................... 52 pwm mode ..................................................... 53 13. analog digital converter .....56 14. serial peripheral interface .59 transmission/receiving timing ...................... 61 the method of serial i/o ................................. 62 the method to test correct transmission ...... 62 15. buzzer function .........................63 16. interrupts ....................................65 interrupt sequence .......................................... 67 multi interrupt .................................................. 69 external interrupt ............................................. 70 17. power saving mode...........................72 operating mode .............................................. 73 stop mode ....................................................... 74 wake-up timer mode ...................................... 75 internal rc-oscillated watchdog timer mode 76 minimizing current consumption .................... 77 18. oscillator circuit.....................79 19. reset ...............................................80 external reset input ........................................ 80 watchdog timer reset ................................... 80 20. power fail processor.............81 21. otp programming.......................83 device configuration area ................. 83 a. control register list .................. i b. instruction ..................................... iii terminology list ................................................ iii instruction map ..................................................iv instruction set ....................................................v c. mask order sheet ........................ xi

GMS81C2112/gms81c2120 june. 2001 ver 1.00 1 GMS81C2112/gms81c2120 cmos single-chip 8-bit microcontroller with a/d converter & vfd driver 1. overview 1.1 description the GMS81C2112 and gms81c2120 are advanced cmos 8-bit microcontroller with 12k/20k bytes of rom. these are a powerful microcontroller which provides a highly flexible and cost effective solution to many vfd applications. these pro- vide the following standard features: 12k/20k bytes of rom, 448 bytes of ram, 8-bit timer/counter, 8-bit a/d converter, 10-bit high speed pwm output, programmable buzzer driving port, 8-bit basic interval timer, 7-bit watch dog timer, serial peripheral interface, on-chip oscillator and clock circuitry. they also come with high voltage i/o pins that can directl y drive a vfd (vacuum fluorescent display). in addition, the GMS81C2112 and gms81c2120 support power saving modes to reduce power consumption. 1.2 features ? 20k/12k bytes rom(eprom) ? 448 bytes of on-chip data ram (including stack area) ? minimum instruction execution time: - 1us at 4mhz (2cycle nop instruction) ? one 8-bit basic interval timer ? one 7-bit watch dog timer ? two 8-bit timer/counters ? 10-bit high speed pwm output ? one 8-bit serial peripheral interface ? two external interrupt ports ? one programmable 6-bit buzzer driving port ? 38 i/o lines - 34 programmable i/o pins (included 21 high-voltage pins max. 40v) - three input only pins: 1 high-voltage pin - one output only pin ? eight interrupt sources - two external sources (int0, int1) - two timer/counter sources (timer0, timer1) - four functional sources (spi,adc,wdt,bit) ? 8-channel 8-bit on-chip analog to digital con- verter ? oscillator: - crystal - ceramic resonator - external r oscillator ? low power dissipation modes - stop mode - wake-up timer mode - standby mode ? operating voltage: 2.7v ~ 5.5v (at 4.5mhz) ? operating frequency: 1mhz ~ 4.5mhz ? enhanced ems improvement power fail processor (noise immunity circuit)enhanced ems improvement power fail processor (noise immunity circuit) device name rom size ram size otp package GMS81C2112 12k bytes 448 bytes - 42sdip, 44mqfp, 40pdip gms81c2120 20k bytes gms87c2120
GMS81C2112/gms81c2120 2 june. 2001 ver 1.00 1.3 development tools the gms81c21xx are supported by a full-featured macro assembler, an in-circuit emulator choice-dr. tm and otp programmers. there are third different type program- mers such as emulator add-on board type, single type, gang type. for mode detail, refer to 21. otp program- ming on page 83. macro assembler operates under the ms-windows 95/98 tm . please contact sales part of hynixsemiconductor. 1.4 ordering information in circuit emulators choice-dr. socket adapter for otp oa87c21xx-42sd (42sdip) oa87c21xx-44qf (44mqfp) pod chpod81c21d-42sd (42sdip) chpod81c21d-40pd (40pdip) assembler hynix macro assembler device name rom size ram size package mask version GMS81C2112 k GMS81C2112 q GMS81C2112 gms81c2120 k gms81c2120 q gms81c2120 12k bytes 12k bytes 12k bytes 20k bytes 20k bytes 20k bytes 448 bytes 448 bytes 448 bytes 448 bytes 448 bytes 448 bytes 42sdip 44mqfp 40pdip 42sdip 44mqfp 40pdip otp version gms87c2120 k gms87c2120 q gms87c2120 20k bytes otp 20k bytes otp 20k bytes otp 448 bytes 448 bytes 448 bytes 42sdip 44mqfp 40pdip
GMS81C2112/gms81c2120 june. 2001 ver 1.00 3 2. block diagram alu interrupt controller data memory 8-bit adc 8-bit counter timer/ program memory data table pc 8-bit basic timer interval watchdog timer pc r5 r2 psw syst em controller timing generator system clock controller clock generator reset x in x out r20~r27 v dd v ss power supply 8-bit serial r53 / sclk r54 / sin r55 / sout r56 / pwm1o/t1o r57 r3 r30~r34 interface buzzer driver r6 r60 / an0 r61 / an1 r62 / an2 r63 / an3 r64 / an4 r65 / an5 r66 / an6 r67 / an7 (448 bytes) 10-bit av dd av ss adc power supply stack pointer r0 r04 r03/buzo r02/ec0 r00/int0 vdisp/ra r05 r06 r07 r01/int1 ra pwm a x y high voltage port
GMS81C2112/gms81c2120 4 june. 2001 ver 1.00 3. pin assignment high voltage port r53 r54 r55 r56 r57 reset xi xo v ss sclk sin sout pwm1o/t1o an0 av ss r60 r61 r62 r63 r64 r65 r66 r67 av dd an1 an2 an3 an4 an5 an6 an7 ra r34 r33 r32 r31 r30 r27 r26 r25 r24 r23 r22 r21 r20 r05 r04 r03 r02 r01 r00 v dd 42sdip 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 buzo ec0 int1 int0 v disp r07 r06 GMS81C2112/20 r57 reset xi xo v ss av ss r60 r61 r62 r63 r64 an1 an0 r27 r26 r25 r24 r23 r22 r21 r20 r07 r06 r05 nc r55 r54 r53 ra r34 r33 r32 r31 r30 r56 r65 r67 av dd v dd r00 r01 r02 r03 r04 nc r66 an5 an6 an7 12 13 14 15 16 17 18 19 20 21 22 41 40 39 38 37 36 35 34 44 43 42 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 44mqfp an2 an3 an4 int0 int1 ec0 buzo sout sin sclk pwm1o/t1o GMS81C2112/20 vdisp
GMS81C2112/gms81c2120 june. 2001 ver 1.00 5 high voltage port r53 r54 r55 r56 r57 reset xi xo v ss sclk sin sout pwm1o/t1o an0 r60 r61 r62 r63 r64 r65 r66 r67 an1 an2 an3 an4 an5 an6 an7 ra r34 r33 r32 r31 r30 r27 r26 r25 r24 r23 r22 r21 r20 r05 r04 r03 r02 r01 r00 v dd 40pdip 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 buzo ec0 int1 int0 v disp r07 r06 GMS81C2112/20
GMS81C2112/gms81c2120 6 june. 2001 ver 1.00 4. package diagram 44mqfp 2.35 max. see detail a 1.03 0.73 0-7 0.25 0.10 1.60 bsc detail a unit: mm 0.45 0.30 0.80 bsc 2.10 1.95 0.23 0.13 10.10 9.90 13.45 12.95 10.10 9.90 13.45 12.95 unit: inch 1.470 1.450 0.020 0.016 0.045 0.035 0.070 bsc 0.140 0.120 min. 0.015 0.550 0.530 0.600 bsc 0-15 42sdip 0 .01 2 0 .0 0 8 0.190 max.
GMS81C2112/gms81c2120 june. 2001 ver 1.00 7 unit: inch 2.075 2.045 0.022 0.015 0.100bsc 0.140 0.120 min. 0.015 0.550 0-15 40pdip 0 .0 1 2 0 .0 0 8 0.200 max. 0.530 0.065 0.045 0.600 bsc
GMS81C2112/gms81c2120 8 june. 2001 ver 1.00 5. pin function v dd : supply voltage. v ss : circuit ground. av dd : supply voltage to the ladder resistor of adc cir- cuit. to enhance the resolution of analog to digital convert- er, use independent power source as well as possible, other than digital power source. av ss : adc circuit ground. reset : reset the mcu. x in : input to the inverting oscillator amplifier and input to the internal clock operating circuit. x out : output from the inverting oscillator amplifier. ra(v disp ) : ra is one-bit high-voltage input only port pin. in addition, ra serves the functions of the v disp special features. v disp is used as a high-voltage input power supply pin when selected by the mask option. r00~r07 : r0 is an 8-bit high-voltage cmos bidirectional i/o port. r0 pins 1 or 0 written to the port direction reg- ister can be used as outputs or inputs. in addition, r0 serves the functions of the various following special fea- tures. r20~r27 : r2 is an 8-bit high-voltage cmos bidirectional i/o port. r2 pins 1 or 0 written to the port direction reg- ister can be used as outputs or inputs. r30~r34 : r3 is a 5-bit high-voltage cmos bidirectional i/o port. r3 pins 1 or 0 written to the port direction reg- ister can be used as outputs or inputs. r53~r57 : r5 is an 5-bit cmos bidirectional i/o port. r5 pins 1 or 0 written to the port direction register can be used as outputs or inputs. in addition, r5 serves the func- tions of the various following special features. r60~r67 : r6 is an 8-bit cmos bidirectional i/o port. r6 pins 1 or 0 written to the port direction register can be used as outputs or inputs. in addition, r6 is shared with the adc input. port pin alternate function ra v disp (high-voltage input power supply) port pin alternate function r00 r01 r02 r03 int0 (external interrupt 0) int1 (external interrupt 1) ec0 (event counter input) buzo (buzzer driver output) port pin alternate function r53 r54 r55 r56 sclk (serial clock) sin (serial data input) sout (serial data output) pwm1o (pwm1 output) t1o (timer/counter 1 output) port pin alternate function r60 r61 r62 r63 r64 r66 r66 r67 an0 (analog input 0) an1 (analog input 1) an2 (analog input 2) an3 (analog input 3) an4 (analog input 4) an5 (analog input 5) an6 (analog input 6) an7 (analog input 7)
GMS81C2112/gms81c2120 june. 2001 ver 1.00 9 pin name in/out function basic alternate v dd - supply voltage v ss - circuit ground ra (v disp ) i(i) 1-bit high-voltage input only port high-voltage input power supply pin reset i reset signal input xin i oscillation input xout o oscillation output r00 (int0) i/o (i) 8-bit high-voltage i/o ports external interrupt 0 input r01 (int1) i/o (i) external interrupt 1 input r02 (ec0) i/o (i) timer/counter 0 external input r03 (buzo) i/o (o) buzzer driving output r04~r07 i/o r20~r27 i/o 8-bit high-voltage i/o ports r30~r34 i/o 5-bit high-voltage i/o ports r53 (sclk) i/o (i/o) 5-bit high-voltage i/o ports serial clock source r54 (sin) i/o (i) serial data input r55 (sout) i/o (o) serial data output r56 (pwm1o/t1o) i/o (o) pwm 1 pulse output /timer/counter 1 out- put r57 i/o r60~r67 (an0~an7) i/o (i) 8-bit general i/o ports analog voltage input av dd - supply voltage input pin for adc av ss - ground level input pin for adc v dd - supply voltage v ss - circuit ground table 5-1 gms81c2120 port function description
GMS81C2112/gms81c2120 10 june. 2001 ver 1.00 6. port structures r57 r00/int0, r01/int1, r02/ec0 r53/sclk r54/sin pin data reg. dir. rd v dd vss reg. data bus mux v dd mask option pull-up tr. pin data reg. dir. rd v dd vdisp reg. data bus selection data reg. ex) int0 alternate function mask option data bus v dd v ss pin data reg. direction reg. rd mux selection sclk output sclk input v dd mask n-mos open drain select option pull-up tr. data bus v dd v ss pin data reg. direction reg. rd selection sin input v dd mask n-mos open drain select option pull-up tr.
GMS81C2112/gms81c2120 june. 2001 ver 1.00 11 r55/sout ra/vdisp r04~r07, r20~r27, r30~r34 reset xin, xout r03/buzo data bus v dd v ss pin data reg. direction reg. rd mux selection sout output ioswin input v dd mask n-mos open drain select ioswb option pull-up tr. rd vdisp data bus v dd mask option pin data reg. dir. rd v dd vdisp reg. data bus mux mask option reset v dd v ss otp :disconnected main :connected xout v dd xin stop mainclk off v ss pin data reg. dir. rd v dd vdisp reg. data bus mux mux selection data reg. secondary function mask option
GMS81C2112/gms81c2120 12 june. 2001 ver 1.00 r56/pwm1o/t1o r60~r67/an0~an7 data bus v dd v ss pin data reg. direction reg. rd mux selection sout output v dd mask n-mos open drain select option pull-up tr. data bus v dd v ss pin data reg. direction reg. rd v dd mask a/d analog converter input mode a/d ch. selection option pull-up tr.
GMS81C2112/gms81c2120 june. 2001 ver 1.00 13 7. electrical characteristics 7.1 absolute maximum ratings supply voltage ............................................. -0.3 to +7.0 v storage temperature .................................... -40 to +85 c voltage on normal voltage pin with respect to ground (v ss ) ..............................................................-0.3 to v dd +0.3 v voltage on high voltage pin with respect to ground (v ss ) ............................................................ -45v to v dd +0.3 v maximum current out of v ss pin .......................... 150 ma maximum current into v dd pin .............................. 80 ma maximum current sunk by (i ol per i/o pin) .......... 20 ma maximum output current sourced by (i oh per i/o pin) ................................................................................... 8 ma maximum current ( s i ol ) ...................................... 100 ma maximum current ( s i oh )........................................ 50 ma note: stresses above those listed under absolute maxi- mum ratings may cause permanent damage to the de- vice. this is a stress rating only and functional operation of the device at any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect device reliability. 7.2 recommended operating conditions 7.3 a/d converter characteristics (t a =25 c, v dd =5v, v ss =0v, av dd =5.12v, av ss =0v @ f xin =4mhz) parameter symbol condition specifications unit min. max. supply voltage v dd f xi = 4.5 mhz 2.7 5.5 v operating frequency f xin v dd = v dd 14.5mhz operating temperature t opr -40 85 c parameter symbol condition specifications unit min. typ. 1 1. data in typ column is at 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. max. analog power supply input voltage range av dd av ss - av dd v analog input voltage range v an av ss -0.3 av dd +0.3 v current following between av dd and av ss i avdd --200ua overall accuracy ca in -- 2lsb non-linearity error n nle -- 2lsb differential non-linearity error n dnle -- 2lsb zero offset error n zoe -- 2lsb full scale error n fse -- 2lsb gain error n nle -- 2lsb conversion time t conv f xin =4mhz --20us
GMS81C2112/gms81c2120 14 june. 2001 ver 1.00 7.4 dc electrical characteristics for standard pins(5v) (v dd = 5.0v 10%, v ss = 0v, t a = -40 ~ 85c, f xin = 4 mhz, vdisp = v dd -40v to v dd ) , parameter pin symbol test condition specification unit min typ. 1 1. data in typ. column is at 4.5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. max input high voltage xin v ih1 external clock 0.9v dd v dd +0.3 v reset ,sin,r55,sclk, int0 & 1,ec0 v ih2 0.8v dd v dd +0.3 r53~r57,r6 v ih3 0.7v dd v dd +0.3 input low voltage xin v il1 external clock -0.3 0.1v dd v reset ,sin,,r55,sclk, int0 & 1,ec0 v il2 -0.3 0.2v dd r53~r57,r6 v il3 -0.3 0.3v dd output high voltage r53~r57,r6,buzo, pwm1o/t1o,sclk,sout v oh i oh = -0.5ma v dd -0.5 v output low voltage r53~r57,r6,buzo, pwm1o/t1o,sclk,sout v ol1 v ol2 i ol = 1.6ma i ol = 10ma 0.4 2 v input high leakage current r53~r57,r6 i ih1 1ua input low leakage current r53~r57,r6 i il1 -1 ua input pull-up current(*option) r53~r57,r6 i pu 50 100 180 ua power fail detect voltage v dd v pfd 2.7 v current dissipation in active mode v dd i dd f xin =4.5mhz 8 ma current dissipation in standby mode v dd i stby f xin =4.5mhz 3 ma current dissipation in stop mode v dd i stop f xin =off f sxin =32.7khz 10 ua hysteresis reset ,sin,r55,sclk, int0 , int1,ec0 v t+ ~v t- 0.4 v internal rc wdt frequency xout t rcwdt 830khz rc oscillation frequency xout f rcosc r= 120k w 1.522.5mhz
GMS81C2112/gms81c2120 june. 2001 ver 1.00 15 7.5 dc electrical characteristics for high-voltage pins (v dd = 5.0v 10%, v ss = 0v, t a = -40 ~ 85c, f xin = 4 mhz, vdisp = v dd -40v to v dd ) parameter pin symbol test condition specification unit min typ. 1 1. data in typ. column is at 4.5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. max input high voltage r0,r2,r30~r34,ra v ih 0.7v dd v dd +0.3 v input low voltage r0,r2,r30~r34,ra v il v dd -40 0.3v dd v output high voltage r0,r2,r30~r34 v oh i oh = -15ma i oh = -10ma i oh = - 4ma v dd -3.0 v dd -2.0 v dd -1.0 v output low voltage r0,r2,r30~r34 v ol vdisp = v dd -40 150k w atv dd - 40 v dd -37 v dd -37 v input high leakage current r0,r2,r30~r34,ra i ih v in =v dd -40v to v dd 20 ua input pull-down current(*option) r0,r2,r30~r34 i pd vdisp=v dd -35v v in =v dd 200 600 1000 ua input high voltage r0,r2,r30~r34,ra v ih 0.7v dd v dd +0.3 v
GMS81C2112/gms81c2120 16 june. 2001 ver 1.00 7.6 ac characteristics (t a =-40~ 85 c, v dd =5v 10% , v ss =0v) figure 7-1 timing chart parameter symbol pins specifications unit min. typ. max. operating frequency f cp xin 1 - 8 mhz external clock pulse width t cpw xin 80 - - ns external clock transition time t rcp, t fcp xin - - 20 ns oscillation stabilizing time t st xin, xout - - 20 ms external input pulse width t epw int0, int1, ec0 2 - - t sys external input pulse transi- tion time t rep, t fep int0, int1, ec0 - - 20 ns reset input width t rst reset 8- - t sys t rcp t fcp xi int0, int1 0.5v v dd -0.5v 0.2v dd resetb t rep t fep 0.2v dd 0.8v dd ec0 t rst t epw t epw 1/f cp t cpw t cpw t sys
GMS81C2112/gms81c2120 june. 2001 ver 1.00 17 7.7 ac characteristics (t a =-40~+85 c, v dd =5v 10%, v ss =0v, f xin =4mhz) figure 7-2 serial i/o timing chart parameter symbol pins specifications unit min. typ. max. serial input clock pulse t scyc sclk 2t sys +200 -8ns serial input clock pulse width t sckw sclk t sys +70 -8ns serial input clock pulse transition time t fsck t rsck sclk - - 30 ns sin input pulse transition time t fsin t rsin sin - - 30 ns sin input setup time (external sclk) t sus sin 100 - - ns sin input setup time (internal sclk) t sus sin 200 - ns sin input hold time t hs sin t sys +70 -ns serial output clock cycle time t scyc sclk 4t sys - 16t sys ns serial output clock pulse width t sckw sclk t sys -30 ns serial output clock pulse transition time t fsck t rsck sclk 30 ns serial output delay time s out sout 100 ns sclk sin 0.2v dd sout 0.2v dd 0.8v dd t scyc t sckw t sckw t rsck t fsck 0.8v dd t sus t hs t ds 0.2v dd 0.8v dd t rsin t fsin
GMS81C2112/gms81c2120 18 june. 2001 ver 1.00 7.8 typical characteristics this graphs and tables provided in this section are for de- sign guidance only and are not tested or guaranteed. in some graphs or tables the data presented are out- side specified operating range (e.g. outside specified v dd range). this is for information only and devices are guaranteed to operate properly only within the specified range. the data presented in this section is a statistical summary of data collected on units from different lots over a period of time. typical represents the mean of the distribution while max or min represents (mean + 3 s ) and (mean - 3 s ) respectively where s is standard deviation i oh - v oh -1.6 -1.2 -0.8 -0.4 0 4.6 4.7 4.8 4.9 5.0 (v) ta=25 c v dd =5.0v (ma) i oh v oh i oh - v oh -1.6 -1.2 -0.8 -0.4 0 3.6 3.7 3.8 3.9 4.0 (v) ta=25 c v dd =4.0v (ma) i oh v oh i oh - v oh -1.6 -1.2 -0.8 -0.4 0 2.6 2.7 2.8 2.9 3.0 (v) ta=25 c v dd =3.0v (ma) i oh v oh i ol - v ol 16 12 8 4 0 0.6 0.8 1.0 1.2 1.4 (v) ta=25 c v dd =5.0v (ma) i ol v ol i ol - v ol 16 12 8 4 0 0.6 0.8 1.0 1.2 1.4 (v) ta=25 c v dd =4.0v (ma) i ol v ol i ol - v ol 16 12 8 4 0 0.6 0.8 1.0 1.2 1.4 (v) ta=25 c v dd =3.0v (ma) i ol v ol i oh - v oh -16 -12 -8 -4 0 1.0 2.0 3.0 4.0 5.0 (v) ta=25 c v dd =5.0v (ma) i oh v oh i oh - v oh -16 -12 -8 -4 0 1.0 2.0 3.0 4.0 5.0 (v) ta=25 c v dd =4.0v (ma) i oh v oh i oh - v oh -16 -12 -8 -4 0 1.0 2.0 3.0 4.0 5.0 (v) ta=25 c v dd =3.0v (ma) i oh v oh r40~r43, r6, r53~r57 buzo, pwm1o/t1o sclk, sout pins r0, r2,ra r30~r34 pins r40~r43, r6, r53~r57 buzo, pwm1o/t1o sclk, sout pins
GMS81C2112/gms81c2120 june. 2001 ver 1.00 19 ta=25 c i dd - v dd 4.0 3.0 2.0 1.0 0 (ma) i dd 23 45 6 v dd (v) normal operation i stop - v dd 2.0 1.5 1.0 0.5 0 ( m a) i dd 23 45 6 v dd (v) stop mode 85 c 25 c -20 c f xin = 4.5mhz 2.5mhz ta=25 c i sby - v dd 4.0 3.0 2.0 1.0 0 (ma) i dd 23 45 6 v dd (v) stand-by mode f xin = 4.5mhz 2.5mhz v dd - v il2 4 3 2 1 0 (v) v il2 23 45 6 v dd (v) v dd - v il1 4 3 2 1 0 (v) v il1 23 45 6 v dd (v) ta=25 c 1 f xin =4.5mhz ta=25 c f xin =4.5mhz v dd - v il3 4 3 2 1 0 (v) v il3 23 45 6 v dd (v) ta=25 c 1 f xin =4.5mhz reset , r55, sin, sclk int0, int1, ec0 pins xin pins v dd - v ih2 4 3 2 1 0 (v) v ih2 23 45 6 v dd (v) v dd - v ih1 4 3 2 1 0 (v) v ih1 23 45 6 v dd (v) ta=25 c 1 f xin =4.5mhz ta=25 c f xin =4.5mhz v dd - v ih3 4 3 2 1 0 (v) v ih3 23 45 6 v dd (v) ta=25 c 1 f xin =4.5mhz reset , r55, sin, sclk int0, int1, ec0 pins xin pins r53~r57, r6 pins r53~r57, r6 pins
GMS81C2112/gms81c2120 20 june. 2001 ver 1.00 8. memory organization the GMS81C2112 and gms81c2120 have separate ad- dress spaces for program memory and data memory. pro- gram memory can only be read, not written to. it can be up to 12k/20k bytes of program memory. data memory can be read and written to up to 448 bytes including the stack area. 8.1 registers this device has six registers that are the program counter (pc), a accumulator (a), two index registers (x, y), the stack pointer (sp), and the program status word (psw). the program counter consists of 16-bit register. figure 8-1 configuration of registers accumulator: the accumulator is the 8-bit general pur- pose register, used for data operation such as transfer, tem- porary saving, and conditional judgement, etc. the accumulator can be used as a 16-bit register with y register as shown below. figure 8-2 configuration of ya 16-bit register x, y registers : in the addressing mode which uses these index registers, the register contents are added to the spec- ified address, which becomes the actual address. these modes are extremely effective for referencing subroutine tables and memory tables. the index registers also have in- crement, decrement, comparison and data transfer func- tions, and they can be used as simple accumulators. stack pointer : the stack pointer is an 8-bit register used for occurrence interrupts and calling out subroutines. stack pointer identifies the location in the stack to be access (save or restore). generally, sp is automatically updated when a subroutine call is executed or an interrupt is accepted. however, if it is used in excess of the stack area permitted by the data memory allocating configuration, the user-processed data may be lost. the stack can be located at any position within 100 h to 1ff h of the internal data memory. the sp is not initialized by hardware, requiring to write the initial value (the loca- tion with which the use of the stack starts) by using the ini- tialization routine. normally, the initial value of ff h is used. note: the stack pointer must be initialized by software be- cause its value is undefined after reset. example: to initialize the sp ldx #0ffh txsp ; sp ? ff h program counter : the program counter is a 16-bit wide which consists of two 8-bit registers, pch and pcl. this counter indicates the address of the next instruction to be executed. in reset state, the program counter has reset rou- tine address (pc h :0ff h , pc l :0fe h ). program status word : the program status word (psw) contains several bits that reflect the current state of the cpu. the psw is described in figure 8-3. it contains the negative flag, the overflow flag, the break flag the half carry (for bcd operation), the interrupt enable flag, the zero flag, and the carry flag. [carry flag c] this flag stores any carry or borrow from the alu of cpu after an arithmetic operation and is also changed by the shift instruction or rotate instruction. [zero flag z] this flag is set when the result of an arithmetic operation or data transfer is "0" and is cleared by any other result. accumulator x register y register stack pointer program counter program status word x a sp y pcl psw pch two 8-bit registers can be used as a "ya" 16-bit register y a y a sp 01 h stack address ( 100 h ~ 1fe h ) bit 15 bit 0 87 hardware fixed 00 h ~ff h
GMS81C2112/gms81c2120 june. 2001 ver 1.00 21 figure 8-3 psw (program status word) register [interrupt disable flag i] this flag enables/disables all interrupts except interrupt caused by reset or software brk instruction. all inter- rupts are disabled when cleared to 0. this flag immedi- ately becomes 0 when an interrupt is served. it is set by the ei instruction and cleared by the di instruction. [half carry flag h] after operation, this is set when there is a carry from bit 3 of alu or there is no borrow from bit 4 of alu. this bit can not be set or cleared except clrv instruction with overflow flag (v). [break flag b] this flag is set by software brk instruction to distinguish brk from tcall instruction with the same vector ad- dress. [direct page flag g] this flag assigns ram page for direct addressing mode. in the direct addressing mode, addressing area is from zero page 00 h to 0ff h when this flag is "0". if it is set to "1", addressing area is assigned 100 h to 1ff h . it is set by setg instruction and cleared by clrg. [overflow flag v] this flag is set to 1 when an overflow occurs as the result of an arithmetic operation involving signs. an overflow occurs when the result of an addition or subtraction ex- ceeds +127(7f h ) or -128(80 h ). the clrv instruction clears the overflow flag. there is no set instruction. when the bit instruction is executed, bit 6 of memory is copied to this flag. [negative flag n] this flag is set to match the sign bit (bit 7) status of the re- sult of a data or arithmetic operation. when the bit in- struction is executed, bit 7 of memory is copied to this flag. n negative flag v g b h i z c msb lsb reset value : 00 h psw overflow flag brk flag carry flag receives zero flag interrupt enable flag carry out half carry flag receives carry out from bit 1 of addition operlands select direct page when g=1, page is selected to page 1
GMS81C2112/gms81c2120 22 june. 2001 ver 1.00 figure 8-4 stack operation at execution of a call/tcall/pcall pcl pch 01fb sp after execution sp before execution 01fc 01fc 01fd 01fe 01fe push down at acceptance of interrupt pcl pch 01fb 01fb 01fc 01fd 01fe 01fe push down psw at execution of ret instruction pcl pch 01fb 01fe 01fc 01fd 01fe 01fc pop up at execution of ret instruction pcl pch 01fb 01fe 01fc 01fd 01fe 01fb pop up psw 0100h 01feh stack depth at execution of push instruction a 01fb 01fd 01fc 01fd 01fe 01fe push down sp after execution sp before execution push a (x,y,psw) at execution of pop instruction a 01fb 01fe 01fc 01fd 01fe 01fd pop up pop a (x,y,psw)
GMS81C2112/gms81c2120 june. 2001 ver 1.00 23 8.2 program memory a 16-bit program counter is capable of addressing up to 64k bytes, but this device has 20k bytes program memory space only physically implemented. accessing a location above ffff h will cause a wrap-around to 0000 h . figure 8-5, shows a map of program memory. after reset, the cpu begins execution from reset vector which is stored in address fffe h and ffff h as shown in figure 8-6. as shown in figure 8-5, each area is assigned a fixed loca- tion in program memory. program memory area contains the user program. figure 8-5 program memory map page call (pcall) area contains subroutine program to reduce program byte length by using 2 bytes pcall in- stead of 3 bytes call instruction. if it is frequently called, it is more useful to save program byte length. table call (tcall) causes the cpu to jump to each tcall address, where it commences the execution of the service routine. the table call service area spaces 2-byte for every tcall: 0ffc0 h for tcall15, 0ffc2 h for tcall14, etc., as shown in figure 8-7. example: usage of tcall the interrupt causes the cpu to jump to specific location, where it commences the execution of the service routine. the external interrupt 0, for example, is assigned to loca- tion 0fffa h . the interrupt service locations spaces 2-byte interval: 0fff8 h and 0fff9 h for external interrupt 1, 0fffa h and 0fffb h for external interrupt 0, etc. any area from 0ff00 h to 0ffff h , if it is not going to be used, its service location is available as general purpose program memory. figure 8-6 interrupt vector area interrupt vector area d000 h feff h ff00 h ffc0 h ffdf h ffe0 h ffff h pcall area b000 h tcall area GMS81C2112, 12k rom gms81c2120, 20k rom lda #5 tcall 0fh ; 1byte instruction :; instead of 3 bytes :; normal call ; ;table call routine ; func_a: lda lrg0 ret ; func_b: lda lrg1 ret ; ;table call add. area ; org 0ffc0h ; tcall address area dw func_a dw func_b 1 2 0ffe0h e2 address vector area memory e4 e6 e8 ea ec ee f0 f2 f4 f6 f8 fa fc fe - - serial communication interface basic interval timer - - - timer/counter 0 interrupt - external interrupt 0 - reset vector area external interrupt 1 watchdog timer interrupt "-" means reserved area. note: timer/counter 1 interrupt - a/d converter
GMS81C2112/gms81c2120 24 june. 2001 ver 1.00 figure 8-7 pcall and tcall memory area pcall ? ? ? ? rel 4f35 pcall 35h tcall ? ? ? ? n 4a tcall 4 0ffc0 h c1 address program memory c2 c3 c4 c5 c6 c7 c8 0ff00 h address pcall area memory 0ffff h pcall area (256 bytes) * means that the brk software interrupt is using same address with tcall0. note: tcall 15 tcall 14 tcall 13 tcall 12 tcall 11 tcall 10 tcall 9 tcall 8 tcall 7 tcall 6 tcall 5 tcall 4 tcall 3 tcall 2 tcall 1 tcall 0 / brk * c9 ca cb cc cd ce cf d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 da db dc dd de df 4f ~ ~ ~ ~ next 35 0ff35 h 0ff00 h 0ffff h 11111111 11010110 01001010 pc: fh fh dh 6h 4a ~ ~ ~ ~ 25 0ffd6 h 0ff00 h 0ffff h d1 next 0ffd7 h ? 0d125 h reverse
GMS81C2112/gms81c2120 june. 2001 ver 1.00 25 example: the usage software example of vector address for gms81c2120. org 0ffe0h dw not_used dw not_used dw sio ; serial interface dw bit_timer ; basic interval timer dw wd_timer ; watchdog timer dw adc ; adc dw not_used dw not_used dw not_used dw not_used dw timer1 ; timer-1 dw timer0 ; timer-0 dw int1 ; int.1 dw int0 ; int.0 dw not_used ; - dw reset ; reset org 0b000h ; gms81c2120(20k)rom start address ; org 0d000h ; GMS81C2112(12k)rom start address ;******************************************* ; main program * ;******************************************* ; reset: di ;disable all interrupts clrg ldx #0 ram_clr: lda #0 ;ram clear(!0000h->!00bfh) sta {x}+ cmpx #0c0h bne ram_clr ; ldx #0ffh ;stack pointer initialize txsp ; ldm r0, #0 ;normal port 0 ldm r0io,#82h ;normal port direction : : : ldm tdr0,#125 ;8us x 125 = 1ms ldm tm0,#0fh ;start timer0, 8us at 4mhz ldm irqh,#0 ldm irql,#0 ldm ienh,#0e0h ;enable timer0, int0, int1 ldm ienl,#0 ldm ieds,#05h ;select falling edge detect on int pin ldm r0func,#03h ;set external interrupt pin(int0, int1) ei ;enable master interrupt : : : : : not_used :nop reti
GMS81C2112/gms81c2120 26 june. 2001 ver 1.00 8.3 data memory figure 8-8 shows the internal data memory space availa- ble. data memory is divided into two groups, a user ram (including stack) and control registers. figure 8-8 data memory map user memory the gms81c21xx have 448 8 bits for the user memory (ram). control registers the control registers are used by the cpu and peripheral function blocks for controlling the desired operation of the device. therefore these registers contain control and status bits for the interrupt system, the timer/ counters, analog to digital converters and i/o ports. the control registers are in address range of 0c0 h to 0ff h . note that unoccupied addresses may not be implemented on the chip. read accesses to these addresses will in gen- eral return random data, and write accesses will have an in- determinate effect. more detailed informations of each register are explained in each peripheral section. note: write only registers can not be accessed by bit ma- nipulation instruction. do not use read-modify-write instruc- tion. use byte manipulation instruction, for example ldm. example; to write at ckctlr ldm clctlr,#09h ;divide ratio( ?16 ) stack area the stack provides the area where the return address is saved before a jump is performed during the processing routine at the execution of a subroutine call instruction or the acceptance of an interrupt. when returning from the processing routine, executing the subroutine return instruction [ret] restores the contents of the program counter from the stack; executing the interrupt return instruction [reti] restores the contents of the pro- gram counter and flags. the save/restore locations in the stack are determined by the stack pointed (sp). the sp is automatically decreased after the saving, and increased before the restoring. this means the value of the sp indicates the stack location number for the next save. refer to figure 8-4 on page 22. user memory control registers or stack area 0000 h 00bf h 00c0 h 00ff h 0100 h 01ff h page0 user memory page1 when g-flag=0, when g-flag=1 this page is selected
GMS81C2112/gms81c2120 june. 2001 ver 1.00 27 note: several names are given at same address. refer to below table. address symbol r/w reset value addressing mode 0c0h 0c1h 0c4h 0c5h 0c6h 0c7h 0cah 0cbh 0cch 0cdh r0 r0io r2 r2io r3 r3io r5 r5io r6 r6io r/w w r/w w r/w w r/w w r/w w undefined 0000_0000 undefined 0000_0000 undefined ---0_0000 undefined 0000_0--- undefined 0000_0000 byte, bit 1 byte 2 byte, bit byte byte, bit byte byte, bit byte byte, bit byte 0d0h 0d1h 0d1h 0d1h 0d2h 0d3h 0d3h 0d4h 0d4h 0d4h 0d5h 0deh tm0 t0 tdr0 cdr0 tm1 tdr1 t1ppr t1 cdr1 t1pdr pwm1hr bur r/w r w r r/w w w r r r/w w w --00_0000 0000_0000 1111_1111 0000_0000 0000_0000 1111_1111 1111_1111 0000_0000 0000_0000 0000_0000 ----_0000 1111_1111 byte, bit byte byte byte byte, bit byte byte byte byte byte, bit byte byte 0e0h 0e1h 0e2h 0e3h 0e4h 0e5h 0e6h 0eah 0ebh 0ech 0ech 0edh 0edh 0efh siom sior ienh ienl irqh irql ieds adcm adcr bitr ckctlr wdtr wdtr pfdr r/w r/w r/w r/w r/w r/w r/w r/w r r w r w r/w 0000_0001 undefined 0000_---- 0000_---- 0000_---- 0000_---- ----_0000 -000_0001 undefined 0000_0000 -001_0111 0000_0000 0111_1111 ----_-100 byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte byte byte byte byte byte, bit 0f4h 0f6h 0f7h 0f9h 0fah 0fbh r0func r5func r6func r5nodr scmr ra w w w w r/w r ----_0000 -0--_---- 0000_0000 0000_0--- ---0_0000 undefined byte byte byte byte byte - 3 table 8-1 control registers 1. "byte, bit" means that register can be addressed by not only bit but byte manipulation instruction. 2. "byte" means that register can be addressed by only byte manipulation instruction. on the other hand, do not use any read-modify-write instruction such as bit manipulation for clearing bit. 3. ra is one-bit high-voltage input only port pin. in addition, ra serves the functions of the vdisp special features. vdisp is used as a high-voltage input power supply pin when selected by the mask option. addr. when read when write timer mode capture mode pwm mode timer mode pwm mode d1h t0 cdr0 - tdr0 - d3h - tdr1 t1ppr d4h t1 cdr1 t1pdr - t1pdr ech bitr ckctlr table 8-2 various register name in same address
GMS81C2112/gms81c2120 28 june. 2001 ver 1.00 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 c0h r0 r0 port data register (bit[7:0]) c1h r0io r0 port direction register (bit[7:0]) c4h r2 r2 port data register (bit[7:0]) c5h r2io r2 port direction register (bit[7:0]) c6h r3 r3 port data register (bit[4:0]) c7h r3io r3 port direction register (bit[4:0]) cah r5 r5 port data register (bit[7:3]) cbh r5io r5 port direction register (bit[7:3]) cch r6 r6 port data register (bit[7:0]) cdh r6io r6 port direction register (bit[7:0]) d0h tm0 - - cap0 t0ck2 t0ck1 t0ck0 t0cn t0st d1h t0/tdr0/ cdr0 timer0 register / timer0 data register / capture0 data register d2h tm1 pol 16bit pwm1e cap1 t1ck1 t1ck0 t1cn t1st d3h tdr1/ t1ppr timer1 data register / pwm1 period register d4h t1/cdr1/ t1pdr timer1 register / capture1 data register / pwm1 duty register d5h pwm1hr pwm1 high register (bit[3:0]) deh bur buck1 buck0 bur5 bur4 bur3 bur2 bur1 bur0 e0h siom pol iosw sm1 sm0 sck1 sck0 siost siosf e1h sior spi data register e2h ienh int0e int1e t0e t1e e3h ienl ade wdte bite spie - - - - e4h irqh int0if int1if t0if t1if e5h irql adif wdtif bitif spiif - - - - e6h ieds ied1h ied1l ied0h ied0l eah adcm - aden ads3 ads2 ads1 ads0 adst adsf ebh adcr adc result data register ech bitr 1 basic interval timer data register ech ckctlr 1 - wakeup rcwdt wdton btcl bts2 bts1 bts0 edh wdtr wdtcl 7-bit watchdog counter register efh pfdr 2 -----pfdispfdmpfds f4h r0func - - - - buzo ec0 int1 int0 table 8-3 control registers of gms81c2120 these registers of shaded area can not be access by bit manipulation instruction as " set1, clr1 ", but should be access by reg - ister operation instruction as " ldm dp,#imm ".
GMS81C2112/gms81c2120 june. 2001 ver 1.00 29 f6h r5func - pwm1o/ t1o - - - - - - f7h r6func an7 an6 an5 an4 an3 an2 an1 an0 f9h r5nodr nodr7 nodr6 nodr5 nodr4 nodr3 - - - fah scmr - - - cs1 cs0 - - mainoff fbhra -------ra0 1.the register bitr and ckctlr are located at same address. address ech is read as bitr, written to ckctlr. 2.the register pfdr only be implemented on devices, not on in-circuit emulator. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 table 8-3 control registers of gms81c2120 these registers of shaded area can not be access by bit manipulation instruction as " set1, clr1 ", but should be access by reg - ister operation instruction as " ldm dp,#imm ".
GMS81C2112/gms81c2120 30 june. 2001 ver 1.00 8.4 addressing mode the gms800 series mcu uses six addressing modes; ? register addressing ? immediate addressing ? direct page addressing ? absolute addressing ? indexed addressing ? register-indirect addressing (1) register addressing register addressing accesses the a, x, y, c and psw. (2) immediate addressing ? ? ? ? #imm in this mode, second byte (operand) is accessed as a data immediately. example: 0435 adc #35h when g-flag is 1, then ram address is defined by 16-bit address which is composed of 8-bit ram paging register (rpr) and 8-bit immediate data. example: g=1 e45535 ldm 35h,#55h (3) direct page addressing ? ? ? ? dp in this mode, a address is specified within direct page. example; g=0 c535 lda 35h ;a ? ram[35h] (4) absolute addressing ? ? ? ? !abs absolute addressing sets corresponding memory data to data, i.e. second byte (operand i) of command becomes lower level address and third byte (operand ii) becomes upper level address. with 3 bytes command, it is possible to access to whole memory area. adc, and, cmp, cmpx, cmpy, eor, lda, ldx, ldy, or, sbc, sta, stx, sty example; 0735f0 adc !0f035h ;a ? rom[0f035h] the operation within data memory (ram) asl, bit, dec, inc, lsr, rol, ror example; addressing accesses the address 0135 h regard- less of g-flag. 35 a+35h+c ? a 04 memory e4 0f100h data 55h ~ ~ ~ ~ data 0135h 35 0f102h 55 0f101h ? data 35 35h 0e551h data ? a ? ~ ~ ~ ~ c5 0e550h 07 0f100h ~ ~ ~ ~ data 0f035h f0 0f102h 35 0f101h ? a+data+c ? a address: 0f035
GMS81C2112/gms81c2120 june. 2001 ver 1.00 31 983501 inc !0135h ;a ? rom[135h] (5) indexed addressing x indexed direct page (no offset) ? ? ? ? {x} in this mode, a address is specified by the x register. adc, and, cmp, eor, lda, or, sbc, sta, xma example; x=15 h , g=1 d4 lda {x} ;acc ? ram[x]. x indexed direct page, auto increment ? ? ? ? {x}+ in this mode, a address is specified within direct page by the x register and the content of x is increased by 1. lda, sta example; g=0, x=35 h db lda {x}+ x indexed direct page (8 bit offset) ? ? ? ? dp+x this address value is the second byte (operand) of com- mand plus the data of -register. and it assigns the mem- ory in direct page. adc, and, cmp, eor, lda, ldy, or, sbc, sta sty, xma, asl, dec, inc, lsr, rol, ror example; g=0, x=0f5 h c645 lda 45h+x y indexed direct page (8 bit offset) ? ? ? ? dp+y this address value is the second byte (operand) of com- mand plus the data of y-register, which assigns memory in direct page. this is same with above (2). use y register instead of x. y indexed absolute ? ? ? ? !abs+y sets the value of 16-bit absolute address plus y-register data as memory.this addressing mode can specify memo- ry in whole area. example; y=55 h 98 0f100h ~ ~ ~ ~ data 135h 01 0f102h 35 0f101h ? data+1 ? data address: 0135 data d4 115h 0e550h data ? a ? ~ ~ ~ ~ data db 35h data ? a ? ~ ~ ~ ~ 36h ? x data 45 3ah 0e551h data ? a ? ~ ~ ~ ~ c6 0e550h 45h+0f5h=13ah
GMS81C2112/gms81c2120 32 june. 2001 ver 1.00 d500fa lda !0fa00h+y (6) indirect addressing direct page indirect ? ? ? ? [dp] assigns data address to use for accomplishing command which sets memory data (or pair memory) by operand. also index can be used with index register x,y. jmp, call example; g=0 3f35 jmp [35h] x indexed indirect ? ? ? ? [dp+x] processes memory data as data, assigned by 16-bit pair memory which is determined by pair data [dp+x+1][dp+x] operand plus x-register data in direct page. adc, and, cmp, eor, lda, or, sbc, sta example; g=0, x=10 h 1625 adc [25h+x] y indexed indirect ? ? ? ? [dp]+y processes memory data as data, assigned by the data [dp+1][dp] of 16-bit pair memory paired by operand in di- rect page plus y-register data. adc, and, cmp, eor, lda, or, sbc, sta example; g=0, y=10 h 1725 adc [25h]+y absolute indirect ? ? ? ? [!abs] the program jumps to address specified by 16-bit absolute address. jmp example; g=0 d5 0f100h data ? a ~ ~ ~ ~ data 0fa55h 0fa00h+55h=0fa55h fa 0f102h 00 0f101h ? 0a 35h jump to ~ ~ ~ ~ 35 0fa00h e3 36h ? 3f 0e30ah next ~ ~ ~ ~ address 0e30ah 05 35h 0e005h ~ ~ ~ ~ 25 0fa00h e0 36h 16 0e005h data ~ ~ ~ ~ a + data + c ? a 25 + x(10) = 35 h ? 05 25h 0e005h + y(10) ~ ~ ~ ~ 25 0fa00h e0 26h ? 17 0e015h data ~ ~ ~ ~ = 0e015h a + data + c ? a
GMS81C2112/gms81c2120 june. 2001 ver 1.00 33 1f25e0 jmp [!0c025h] 25 0e025h jump to ~ ~ ~ ~ e0 0fa00h e7 0e026h ? 25 0e725h next ~ ~ ~ ~ 1f program memory address 0e30ah
GMS81C2112/gms81c2120 34 june. 2001 ver 1.00 9. i/o ports the gms81c21xx has five ports (r0, r2, r3, r5, and r6).these ports pins may be multiplexed with an alternate function for the peripheral features on the device. all pins have data direction registers which can define these ports as output or input. a 1 in the port direction register configure the corresponding port pin as output. conversely, write 0 to the corresponding bit to specify it as input pin. for example, to use the even numbered bit of r0 as output ports and the odd numbered bits as input ports, write 55 h to address 0c1 h (r0 port direction reg- ister) during initial setting as shown in figure 9-1. all the port direction registers in the gms81c2120 have 0 written to them by reset function. on the other hand, its in- itial status is input. figure 9-1 example of port i/o assignment ra(vdisp) register: ra is one-bit high-voltage input only port pin. in addition, ra serves the functions of the v disp special features. v disp is used as a high-voltage input power supply pin when selected by the mask option. r0 and r0io register: r0 is an 8-bit high-voltage cmos bidirectional i/o port (address 0c0 h ). each port can be set individually as input and output through the r0io register (address 0c1 h ). each port can directly drive a vacuum flu- orescent display. r03 port is multiplexed with buzzer out- put port(buzo), r02 port is multiplexed with event counter input port (ec0), and r01~r00 are multiplexed with external interrupt input port(int1, int0) .the control register r0func (address f4 h ) controls to select alternate function. after reset, this value is "0", port may be used as general i/o ports. to select alternate func- tion such as buzzer output, external event counter input and external interrupt input, write "1" to the correspond- ing bit of r0func. regardless of the direction register r0io, r0func is selected to use as alternate functions, port pin can be used as a corresponding alternate features (buzo, ec0, int1, int0) port pin alternate function ra v disp (high-voltage input power supply) i : input port write "55 h " to port r0 direction register 0 1 0 1 0 1 0 1 i o i o i o i o r0 data r1 data r0 direction r1 direction 0c0 h 0c1 h 0c2 h 0c3 h 76543210 bit 76543210 port o : output port ra data register ra address: 0fb h reset value: undefined ra0 input data port pin alternate function r00 r01 r02 r03 int0 (external interrupt 0 input port) int1 (external interrupt 1 input port) ec0 (event counter input port) buzo (buzzer output port) r0 data register r0 address: 0c0 h reset value: undefined r07 r06 r05 r04 r03 r02 r01 r00 port direction r0 direction register r0io address : 0c1 h reset value : 00 h 0: input 1: output input / output data r0 function selection register r0func address : 0f4 h reset value : ----0000 b 0: r00 1: int0 0 0: r01 1: int1 0: r02 1: buzo 0: r03 1: ec0 1 2 3 - - - -
GMS81C2112/gms81c2120 june. 2001 ver 1.00 35 r2 and r2io register: r2 is an 8-bit high-voltage cmos bidirectional i/o port (address 0c4 h ). each port can be set individually as input and output through the r2io register (address 0c5 h ). each port can directly drive a vacuum flu- orescent display. r3 and r3io register: r3 is a 5-bit high-voltage cmos bidirectional i/o port (address 0c6 h ). each port can be set individually as input and output through the r3io register (address 0c7 h ). r5 and r5io register: r5 is an 5-bit bidirectional i/o port (address 0ca h ). each pin can be set individually as input and output through the r5io register (address 0cb h ).in addition, port r5 is multiplexed with pulse width modulator (pwm). the control register r5func (address 0f6 h ) controls to select pwm function.after reset, the r5io register value is "0", port may be used as general i/o ports. to select pwm function, write "1" to the corresponding bit of r5func. the control register r5nodr (address 0f9 h ) controls to select n-mos open drain port. to select n-mos open drain port, write "1" to the corresponding bit of r5func. r6 and r6io register: r6 is an 8-bit bidirectional i/o port (address 0cc h ). each port can be set individually as input and output through the r6io register (address 0cd h ). r67~r60 ports are multiplexed with analog input port. the control register r6func (address 0f7 h ) controls to select alternate function. after reset, this value is "0", port may be used as general i/o ports. to select alternate func- port pin alternate function r56 pwm1 data output timer 1 data output r2 data register r2 address: 0c4 h reset value: undefined r27 r26 r25 r24 r23 r22 r21 r20 port direction r2 direction register r2io address : 0c5 h reset value : 00 h 0: input 1: output input / output data r3 data register r3 address: 0c6 h reset value: undefined - - - r34 r33 r32 r31 r30 port direction r3 direction register r3io address : 0c7 h reset value : ---00000 b 0: input 1: output input / output data - - - port pin alternate function r60 r61 r62 r63 r64 r65 r66 r67 an0 (adc input 0) an1 (adc input 1) an2 (adc input 2) an3 (adc input 3) an4 (adc input 4) an5 (adc input 5) an6 (adc input 6) an7 (adc input 7) r5 data register r5 address: 0ca h reset value: undefined r57 r56 r55 r54 r53 - - - r5 direction register r5io address : 0cb h reset value : 00000--- b input / output data r5 function selection register r5func address : 0f6 h reset value : -0------ b 0: r56 1: - - - - - - 6 - r5 n-mos open drain r5nodr address: 0f9 h reset value: 00000--- b n-mos open drain selection selection register 0: disable 1: enable port direction 0: input 1: output pwm1o/t1o
GMS81C2112/gms81c2120 36 june. 2001 ver 1.00 tion such as analog input, write "1" to the corresponding bit of r6func. regardless of the direction register r6io, r6func is selected to use as alternate functions, port pin can be used as a corresponding alternate features (an7~an0) r6 function selection register r6func address : 0f7 h reset value : 00 h 0: r60 1: an0 0 0: r61 1: an1 0: r63 1: an3 0: r62 1: an2 1 2 3 4 5 6 7 0: r65 1: an5 0: r64 1: an4 0: r66 1: an6 0: r67 1: an7 r6 data register r6 address: 0cc h reset value: undefined r67 r66 r65 r64 r63 r62 r61 r60 input / output data r6 direction register r6io address : 0cd h reset value : 00 h port direction 0: input 1: output
GMS81C2112/gms81c2120 june. 2001 ver 1.00 37 10. basic interval timer the gms81c21xx has one 8-bit basic interval timer that is free-run, can not stop. block diagram is shown in figure 10-1. in addition, the basic interval timer generates the time base for watchdog timer counting. it also provides a basic interval timer interrupt (bitif). the 8-bit basic interval timer register (bitr) is increased every internal count pulse which is divided by prescaler. since prescaler has divided ratio by 8 to 1024, the count rate is 1/8 to 1/1024 of the oscillator frequency. as the count overflows from ff h to 00 h , this overflow causes to generate the basic interval timer interrupt. the bitif is in- terrupt request flag of basic interval timer. the basic in- terval timer is controlled by the clock control register (ckctlr) shown in figure 10-2. when write "1" to bit btcl of ckctlr, bitr register is cleared to "0" and restart to count-up. the bit btcl be- comes "0" after one machine cycle by hardware. if the stop instruction executed after writing "1" to bit wakeup of ckctlr, it goes into the wake-up timer mode. in this mode, all of the block is halted except the os- cillator, prescaler (only fxin ? 2048) and timer0. if the stop instruction executed after writing "1" to bit rcwdt of ckctlr, it goes into the internal rc oscillat- ed watchdog timer mode. in this mode, all of the block is halted except the internal rc oscillator, basic interval timer and watchdog timer. more detail informations are explained in power saving function. the bit wdton de- cides watchdog timer or the normal 7-bit timer. source clock can be selected by lower 3 bits of ckctlr. bitr and ckctlr are located at same address, and ad- dress 0ec h is read as a bitr, and written to ckctlr. figure 10-1 block diagram of basic interval timer mux basic interval bitr select input clock 3 basic interval timer source clock 8-bit up-counter bts[2:0] btcl ? 1024 ? 512 ? 256 ? 128 ? 64 ? 32 ? 16 ? 8 to watchdog timer (wdtck) ckctlr clear overflow internal bus line clock control register [0ec h ] [0ec h ] bitif read x in pin prescaler timer interrupt internal rc osc rcwdt 1 0 wakeup stop
GMS81C2112/gms81c2120 38 june. 2001 ver 1.00 table 10-1 basic interval timer interrupt time figure 10-2 bitr: basic interval timer mode register example 1: basic interval timer interrupt request flag is generated every 4.096ms at 4mhz. : ldm ckctlr,#03h set1 bite ei : example 2: basic interval timer interrupt request flag is generated every 1.024ms at 4mhz. : ldm ckctlr,#01h set1 bite ei : ckctlr [2:0] source clock interrupt (overflow) period (ms) @ f xin = 4mhz 000 001 010 011 100 101 110 111 f xin ? 8 f xin ? 16 f xin ? 32 f xin ? 64 f xin ? 128 f xin ? 256 f xin ? 512 f xin ? 1024 0.512 1.024 2.048 4.096 8.192 16.384 32.768 65.536 btcl 76543210 rcwdt - bts1 basic interval timer source clock select 000: f xin ? 8 001: f xin ? 16 010: f xin ? 32 011: f xin ? 64 100: f xin ? 128 101: f xin ? 256 110: f xin ? 512 111: f xin ? 1024 clear bit 0: normal operation (free-run) 1: clear 8-bit counter (bitr) to 0. this bit becomes 0 automatically initial value: -001 0111 b address: 0ec h after one machine cycle, and starts counting. ckctlr initial value: undefined address: 0ec h bitr both register are in same address, when write, to be a ckctlr, when read, to be a bitr. caution: 8-bit free-run binary counter wdton bts0 bts2 btcl btcl 76543210 0: operate as a 7-bit general timer 1: enable watchdog timer operation see the section watchdog timer. wakeup 0: disable wake-up timer 1: enable wake-up timer 0: disable internal rc watchdog timer 1: enable internal rc watchdog timer
GMS81C2112/gms81c2120 june. 2001 ver 1.00 39 11. watchdog timer the watchdog timer rapidly detects the cpu malfunction such as endless looping caused by noise or the like, and re- sumes the cpu to the normal state. the watchdog timer signal for detecting malfunction can be selected either a reset cpu or a interrupt request. when the watchdog timer is not being used for malfunc- tion detection, it can be used as a timer to generate an in- terrupt at fixed intervals. the purpose of the watchdog timer is to detect the malfunction (runaway) of program due to external noise or other causes and return the opera- tion to the normal condition. the watchdog timer has two types of clock source. the first type is an on-chip rc oscillator which does not require any external components. this rc oscillator is sep- arate from the external oscillator of the xin pin. it means that the watchdog timer will run, even if the clock on the xin pin of the device has been stopped, for example, by en- tering the stop mode. the other type is a prescaled system clock. the watchdog timer consists of 7-bit binary counter and the watchdog timer data register. when the value of 7-bit binary counter is equal to the lower 7 bits of wdtr, the interrupt request flag is generated. this can be used as wdt interrupt or reset the cpu in accordance with the bit wdton. note: because the watchdog timer counter is enabled af- ter clearing basic interval timer, after the bit wdton set to "1", maximum error of timer is depend on prescaler ratio of basic interval timer. the 7-bit binary counter is cleared by setting wdtcl(bit7 of wdtr) and the wdtcl is cleared automatically after 1 machine cycle. the rc oscillated watchdog timer is activated by setting the bit rcwdt as shown below. ldm ckctlr,#3fh; enable the rc-osc wdt ldm wdtr,#0ffh; set the wdt period stop ; enter the stop mode nop nop ; rc-osc wdt running : the rcwdt oscillation period is vary with temperature, vdd and process variations from part to part (approxi- mately, 40~120us). the following equation shows the rcwdt oscillated watchdog timer time-out. t rcwdt =clk rcwdt 2 8 [ wdtr.6~0]+(clk rcwdt 2 8 )/2 where, clk rcwdt = 40~120us in addition, this watchdog timer can be used as a simple 7- bit timer by interrupt wdtif. the interval of watchdog timer interrupt is decided by basic interval timer. interval equation is as below. t wdt = [wdtr.6~0] interval of bit figure 11-1 block diagram of watchdog timer to reset cpu basic interval timer count enable watchdog 7-bit compare data comparator watchdog timer interrupt clear clear wdtif counter (7-bit) wdtcl 0 1 wdton in ckctlr [0ec h ] overflow watchdog timer register wdtr internal bus line 7 [0ed h ] source
GMS81C2112/gms81c2120 40 june. 2001 ver 1.00 watchdog timer control figure 11-2 shows the watchdog timer control register. the watchdog timer is automatically disabled after reset. the cpu malfunction is detected during setting of the de- tection time, selecting of output, and clearing of the binary counter. clearing the binary counter is repeated within the detection time. if the malfunction occurs for any cause, the watchdog tim- er output will become active at the rising overflow from the binary counters unless the binary counter is cleared. at this time, when wdton=1, a reset is generated, which drives the reset pin to low to reset the internal hardware. when wdton=0, a watchdog timer interrupt (wdtif) is generated. the watchdog timer temporarily stops counting in the stop mode, and when the stop mode is released, it au- tomatically restarts (continues counting). figure 11-2 wdtr: watchdog timer data register example: sets the watchdog timer detection time to 0.5 sec at 4.19mhz 76543210 clear count flag 0: free-run count initial value: 0111_1111 b address: 0ed h wdtr ww ww 1: when the wdtcl is set to "1", binary counter is cleared to 0. and the wdtcl becomes 0 automatically after one machine cycle. counter count up again. 7-bit compare data wwww note: the wdton bit is in register ckctlr. wdtcl ldm ckctlr,#3fh ; select 1/2048 clock source , wdton ? 1, clear counter ldm wdtr,#04fh ldm wdtr,#04fh ; clear counter : : : : ldm wdtr,#04fh ; clear counter : : : : ldm wdtr,#04fh ; clear counter within wdt detection time within wdt detection time
GMS81C2112/gms81c2120 june. 2001 ver 1.00 41 enable and disable watchdog watchdog timer is enabled by setting wdton (bit 4 in ckctlr) to 1. wdton is initialized to 0 during re- set and it should be set to 1 to operate after reset is re- leased. example: enables watchdog timer for reset : ldm ckctlr,#xx1x_xxxxb; wdton ? 1 : : the watchdog timer is disabled by clearing bit 5 (wd- ton) of ckctlr. the watchdog timer is halted in stop mode and restarts automatically after stop mode is re- leased. watchdog timer interrupt the watchdog timer can be also used as a simple 7-bit tim- er by clearing bit5 of ckctlr to 0. the interval of watchdog timer interrupt is decided by basic interval tim- er. interval equation is shown as below. the stack pointer (sp) should be initialized before using the watchdog timer output as an interrupt source. example: 7-bit timer interrupt set up. ldm ckctlr,#xx0xxxxxb; wdton ? 0 ldm wdtr,#7fh ; wdtcl ? 1 : figure 11-3 watchdog timer timing if the watchdog timer output becomes active, a reset is gen- erated, which drives the reset pin low to reset the inter- nal hardware. the main clock oscillator also turns on when a watchdog timer reset is generated in sub clock mode. t wdtr interval of bit = 2 3 n source clock binary-counter wdtr wdtif interrupt wdtr ? "0100_0011 b " 1 0 match detect counter clear 1 2 30 bit overflow 3 wdt reset reset
GMS81C2112/gms81c2120 42 june. 2001 ver 1.00 12. timer/event counter the gms81c21xx has two timer/counter registers. each module can generate an interrupt to indicate that an event has occurred (i.e. timer match). timer 0 and timer 1 are can be used either two 8-bit tim- er/counter or one 16-bit timer/counter with combine them. in the "timer" function, the register is increased every in- ternal clock input. thus, one can think of it as counting in- ternal clock input. since a least clock consists of 2 and most clock consists of 2048 oscillator periods, the count rate is 1/2 to 1/2048 of the oscillator frequency in timer0. and timer1 can use the same clock source too. in addition, timer1 has more fast clock source (1/1 to 1/8). in the counter function, the register is increased in re- sponse to a 1-to-0 (falling edge) or 0-to-1(rising edge) tran- sition at its corresponding external input pin, ec0. in addition the capture function, the register is increased in response external or internal clock sources same with timer or counter function. when external clock edge input, the count register is captured into capture data register cdrx. timer1 is shared with "pwm" function and "compare out- put" function it has seven operating modes: "8-bit timer/counter", "16- bit timer/counter", "8-bit capture", "16-bit capture", "8-bit compare output", "16-bit compare output" and "10-bit pwm" which are selected by bit in timer mode register tm0 and tm1 as shown in figure 12-1 and table 12-1. 16bit cap0 cap1 pwm1e t0ck [2:0] t1ck [1:0] pwm1o timer 0 timer 1 0 0 0 0 xxx xx 0 8-bit timer 8-bit timer 0 0 1 0 111 xx 0 8-bit event counter 8-bit capture 0 1 0 0 xxx xx 1 8-bit capture (internal clock) 8-bit compare output 0 x 0 1 xxx xx 1 8-bit timer/counter 10-bit pwm 1 0 0 0 xxx 11 0 16-bit timer 1 0 0 0 111 11 0 16-bit event counter 1 1 x 0 xxx 11 0 16-bit capture (internal clock) 1 0 0 0 xxx 11 1 16-bit compare output table 12-1 operating modes of timer0 and timer1
GMS81C2112/gms81c2120 june. 2001 ver 1.00 43 figure 12-1 tm0, tm1 registers btcl 76543210 16bit pol t1cn initial value: 00 h address: 0d2 h tm1 t1st t1ck0 t1ck1 pwm1e cap1 bit name bit position description pol tm1.7 0: pwm duty active low 1: pwm duty active high 16bit tm1.6 0: 8-bit mode 1: 16-bit mode pwmie tm1.5 0: disable pwm 1: enable pwm cap1 tm1.4 0: timer/counter mode 1: capture mode selection flag t1ck1 t1ck0 tm1.3 tm1.2 00: 8-bit timer, clock source is f xin 01: 8-bit timer, clock source is f xin ? 2 10: 8-bit timer, clock source is f xin ? 8 11: 8-bit timer, clock source is using the the timer 0 clock t0cn tm1.1 0: stop the timer 1: a logic 1 starts the timer. t0st tm1.0 0: when cleared, stop the counting. 1: when set, timer 0 count register is cleared and start again. btcl 543210 - - t0cn initial value: --000000 b address: 0d0 h tm0 t0st t0ck0 t0ck1 cap0 t0ck2 bit name bit position description cap0 tm0.5 0: timer/counter mode 1: capture mode selection flag t0ck2 t0ck1 t0ck0 tm0.4 tm0.3 tm0.2 000: 8-bit timer, clock source is f xin ? 2 001: 8-bit timer, clock source is f xin ? 4 010: 8-bit timer, clock source is f xin ? 8 011: 8-bit timer, clock source is f xin ? 32 100: 8-bit timer, clock source is f xin ? 128 101: 8-bit timer, clock source is f xin ? 512 110: 8-bit timer, clock source is f xin ? 2048 111: ec0 (external clock) t0cn tm0.1 0: stop the timer 1: a logic 1 starts the timer. t0st tm0.0 0: when cleared, stop the counting. 1: when set, timer 0 count register is cleared and start again. 76543210 initial value: undefined address: 0d1 h tdr0 read: count value read write: compare data write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 76543210 initial value: undefined address: 0d3 h tdr1 r/w r/w r/w r/w r/w r/w r/w r/w
GMS81C2112/gms81c2120 44 june. 2001 ver 1.00 12.1 8-bit timer / counter mode the gms81c21xx has two 8-bit timer/counters, timer 0, timer 1 as shown in figure 12-2. the "timer" or "counter" function is selected by mode reg- isters tmx as shown in figure 12-1 and table 12-1. to use as an 8-bit timer/counter mode, bit cap0 of tm0 is cleared to "0" and bits 16bit of tm1 should be cleared to 0(table 12-1). figure 12-2 8-bit timer/counter 0, 1 ec0 pin ? 2 ? 4 ? 8 xin pin mux prescaler clear 0: stop 1: clear and start t0st t0ck[2:0] 111 000 001 010 t0cn mux t1if clear 0: stop 1: clear and start t1st t1ck[1:0] 11 00 01 timer 1 interrupt ? 1 ? 2 ? 8 tdr0 (8-bit) tdr1 (8-bit) t1 (8-bit) t0 (8-bit) comparator comparator timer 0 timer 1 t1o pin f/f btcl 76543210 - -t0cn initial value: --000000 b address: 0d0 h tm0 t0st t0ck0 t0ck1 cap0 t0ck2 -- xx x x x means dont care ? ? ? 512 ? 2048 011 100 101 110 t0if timer 0 interrupt t0o pin f/f t1cn 10 initial value: 00 h address: 0d2 h tm1 x means dont care 0x btcl 76543210 16bit pol t1cn t1st t1ck0 t1ck1 pwm1e cap1 x0 x x x x 00 edge detector
GMS81C2112/gms81c2120 june. 2001 ver 1.00 45 example 1: timer0 = 2ms 8-bit timer mode at 4mhz timer1 = 0.5ms 8-bit timer mode at 4mhz ldm tdr0,#250 ldm tdr1,#250 ldm tm0,#0000_1111b ldm tm1,#0000_1011b set1 t0e set1 t1e ei example 2: timer0 = 8-bit event counter mode timer1 = 0.5ms 8-bit timer mode at 4mhz ldm tdr0,#250 ldm tdr1,#250 ldm tm0,#0001_1111b ldm tm1,#0000_1011b set1 t0e set1 t1e ei note: the contents of timer data register tdrx should be initialized 1 h ~ff h , not 0 h , because it is undefined after re- set. these timers have each 8-bit count register and data regis- ter. the count register is increased by every internal or ex- ternal clock input. the internal clock has a prescaler divide ratio option of 2, 4, 8, 32,128, 512, 2048 selected by con- trol bits t0ck[2:0] of register (tm0) and 1, 2, 8 selected by control bits t1ck[1:0] of register (tm1). in the timer 0, timer register t0 increases from 00 h until it matches tdr0 and then reset to 00 h . the match output of timer 0 generates timer 0 interrupt (latched in t0if bit). as tdrx and tx register are in same address, when reading it as a tx, written to tdrx. in counter function, the counter is increased every 0-to- 1(1-to-0) (rising & falling edge) transition of ec0 pin. in order to use counter function, the bit ec0 of the r0 func- tion selection register (r0func.2) is set to "1". the timer 0 can be used as a counter by pin ec0 input, but timer 1 can not.
GMS81C2112/gms81c2120 46 june. 2001 ver 1.00 8-bit timer mode in the timer mode, the internal clock is used for counting up. thus, you can think of it as counting internal clock in- put. the contents of tdr n are compared with the contents of up-counter, t n . if match is found, a timer 1 interrupt (t1if) is generated and the up-counter is cleared to 0. counting up is resumed after the up-counter is cleared. as the value of tdr n is changeable by software, time in- terval is set as you want figure 12-3 timer mode timing chart figure 12-4 timer count example 0 n-2 2 0 n 3 n-1 n source clock up-counter tdr1 t1if interrupt start count 1 23 1 4 match detect counter clear ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ timer 1 (t1if) interrupt tdr1 time occur interrupt occur interrupt occur interrupt interrupt period up-count ~ ~ ~ ~ 0 1 2 3 4 5 6 7a 7d 7c count pulse = 8 m s x 125 7b match example: make 2ms interrupt using by timer0 at 4mhz ldm tm0,#0fh ; divide by 32 ldm tdr0,#125 ; 8us x 125= 1ms set1 t0e ; enable timer 0 interrupt ei ; enable master interrupt period when tdr0 = 125 d = 7d h f xin = 4 mhz interrupt period = 4 10 6 hz 1 32 125 = 1 ms tm0 = 0000 1111 b (8-bit timer mode, prescaler divide ratio = 32) 8 m s (tdr0 = t0) 7d 0
GMS81C2112/gms81c2120 june. 2001 ver 1.00 47 8-bit event counter mode in this mode, counting up is started by an external trigger. this trigger means falling edge or rising edge of the ec0 pin input. source clock is used as an internal clock selected with timer mode register tm0. the contents of timer data register tdr0 is compared with the contents of the up- counter t0. if a match is found, an timer interrupt request flag t0if is generated, and the counter is cleared to 0. the counter is restart and count up continuously by every falling edge or rising edge of the ec0 pin input. the maximum frequency applied to the ec0 pin is f xin /2 [hz]. in order to use event counter function, the bit 2 of the r5 function register (r5func.2) is required to be set to 1. after reset, the value of timer data register tdr0 is unde- fined, it should be initialized to between 1 h ~ff h not to "0"the interval period of timer is calculated as below equation. figure 12-5 event counter mode timing chart figure 12-6 count operation of timer / event counter period (sec) 1 f xin ---------- - 2 divide ratio tdr0 = 0 1 2 1 0 n 2 ~ ~ ~ ~ ~ ~ n-1 n ~ ~ ~ ~ ~ ~ ec n pin input up-counter tdr1 t1if interrupt start count timer 1 (t1if) interrupt tdr1 time occur interrupt occur interrupt stop clear & start disable enable start & stop t1st t1cn control count up-count ~ ~ ~ ~ t1st = 0 t1st = 1 t1cn = 0 t1cn = 1
GMS81C2112/gms81c2120 48 june. 2001 ver 1.00 12.2 16-bit timer / counter mode the timer register is being run with 16 bits. a 16-bit timer/ counter register t0, t1 are increased from 0000 h until it matches tdr0, tdr1 and then resets to 0000 h . the match output generates timer 0 interrupt not timer 1 in- terrupt. the clock source of the timer 0 is selected either internal or external clock by bit t0ck[2:0]. in 16-bit mode, the bits t1ck[1:0] and 16bit of tm1 should be set to "1" respectively. figure 12-7 16-bit timer/counter clear 0: stop 1: clear and start t0st t0cn tdr1 + tdr0 comparator timer 0 + timer 1 ? timer 0 (16-bit) higher byte lower byte (16-bit) compare data t1 + t0 (16-bit) 1 0 (not timer 1 interrupt) edge btcl 76543210 - -t0cn initial value: --000000 b address: 0d0 h tm0 t0st t0ck0 t0ck1 cap0 t0ck2 -- xx x x x means dont care initial value: 00 h address: 0d2 h tm1 x means dont care 0x btcl 76543210 16bit pol t1cn t1st t1ck0 t1ck1 pwm1e cap1 x1 x x 1 1 00 ec0 pin ? 2 ? 4 ? 8 xin pin mux prescaler t0ck[2:0] 111 000 001 010 ? ? ? 512 ? 2048 011 100 101 110 detector t0if timer 0 interrupt t0o pin f/f
GMS81C2112/gms81c2120 june. 2001 ver 1.00 49 12.3 8-bit compare output (16-bit) the gms81c21xx has a function of timer compare out- put. to pulse out, the timer match can goes to port pin(t0o, t1o) as shown in figure 12-2 and figure 12-7. thus, pulse out is generated by the timer match. these op- eration is implemented to pin, t0o, pwm1o/t1o. in this mode, the bit pwm1o/t1o of r5 function register (r5func.6) should be set to "1", and the bit pwm1e of timer1 mode register (tm1) should be set to "0". in addi- tion, 16-bit compare output mode is available, also. this pin output the signal having a 50 : 50 duty square wave, and output frequency is same as below equation. 12.4 8-bit capture mode the timer 0 capture mode is set by bit cap0 of timer mode register tm0 (bit cap1 of timer mode register tm1 for timer 1) as shown in figure 12-8. as mentioned above, not only timer 0 but timer 1 can also be used as a capture mode. the timer/counter register is increased in response inter- nal or external input. this counting function is same with normal timer mode, and timer interrupt is generated when timer register t0 (t1) increases and matches tdr0 (tdr1). this timer interrupt in capture mode is very useful when the pulse width of captured signal is more wider than the maximum period of timer. for example, in figure 12-10, the pulse width of captured signal is wider than the timer data value (ff h ) over 2 times. when external interrupt is occurred, the captured value (13 h ) is more little than wanted value. it can be ob- tained correct value by counting the number of timer over- flow occurrence. timer/counter still does the above, but with the added fea- ture that a edge transition at external input intx pin causes the current value in the timer x register (t0,t1), to be cap- tured into registers cdrx (cdr0, cdr1), respectively. after captured, timer x register is cleared and restarts by hardware. note: the cdrx, tdrx and tx are in same address. in the capture mode, reading operation is read the cdrx, not tx because path is opened to the cdrx, and tdrx is only for writing operation. it has three transition modes: "falling edge", "rising edge", "both edge" which are selected by interrupt edge selection register ieds (refer to external interrupt section). in ad- dition, the transition at intx pin generate an interrupt. f comp oscillation frequency 2 prescaler value tdr 1 ) + ( --------------------------------------------------------------------------------- =
GMS81C2112/gms81c2120 50 june. 2001 ver 1.00 . figure 12-8 8-bit capture mode int0if 0: stop 1: clear and start t0st int0 interrupt t0cn cdr0 (8-bit) t0 (8-bit) 01 10 11 capture ieds[1:0] ec0 pin ? 2 ? 4 ? 8 xin pin mux prescaler t0ck[2:0] 111 000 001 010 mux t1ck[1:0] 11 00 01 ? 1 ? 2 ? 8 ? ? ? 512 ? 2048 011 100 101 110 10 int0 pin int1if 0: stop 1: clear and start t1st int1 interrupt t1cn cdr1 (8-bit) t1 (8-bit) 01 10 11 capture ieds[1:0] int1 pin btcl 76543210 - -t0cn initial value: --000000 b address: 0d0 h tm0 t0st t0ck0 t0ck1 cap0 t0ck2 -- xx x x x means dont care initial value: 00 h address: 0d2 h tm1 x means dont care 1x btcl 76543210 16bit pol t1cn t1st t1ck0 t1ck1 pwm1e cap1 x0 x x x x 01 edge detector clear clear
GMS81C2112/gms81c2120 june. 2001 ver 1.00 51 figure 12-9 input capture operation figure 12-10 excess timer overflow in capture mode ~ ~ ext. int0 pin interrupt request t0 time up - coun t ~ ~ ~ ~ 0 1 2 3 4 5 6 7 8 9 n n-1 capture ( timer stop ) clear & start interrupt interval period delay ( int0f ) ext. int0 pin interrupt request ( int0f ) this value is loaded to cdr0 interrupt interval period = ff h + 01 h + ff h +01 h + 13 h = 213 h ff h ff h ext. int0 pin interrupt request ( int0f ) 00 h 00 h interrupt request ( t0f ) t0 13 h
GMS81C2112/gms81c2120 52 june. 2001 ver 1.00 12.5 16-bit capture mode 16-bit capture mode is the same as 8-bit capture, except that the timer register is being run will 16 bits. the clock source of the timer 0 is selected either internal or external clock by bit t0ck2, t0ck1 and t0ck0. in 16-bit mode, the bits t1ck1,t1ck0 and 16bit of tm1 should be set to "1" respectively. figure 12-11 16-bit capture mode 0: stop 1: clear and start t0st t0cn capture cdr1 + cdr0 higher byte lower byte (16-bit) capture data tdr1 + tdr0 (16-bit) int0if int0 interrupt 01 10 11 ieds[1:0] ec0 pin ? 2 ? 4 ? 8 xin pin mux prescaler t0ck[2:0] 111 000 001 010 ? ? ? 512 ? 2048 011 100 101 110 int0 pin btcl 76543210 - -t0cn initial value: --000000 b address: 0d0 h tm0 t0st t0ck0 t0ck1 cap0 t0ck2 -- xx x x x means dont care initial value: 00 h address: 0d2 h tm1 x means dont care 1 x btcl 76543210 16bit pol t1cn t1st t1ck0 t1ck1 pwm1e cap1 x1 x x 1 1 0x edge detector clear
GMS81C2112/gms81c2120 june. 2001 ver 1.00 53 example 1: timer0 = 16-bit timer mode, 0.5s at 4mhz ldm tm0,#0000_1111b;8us ldm tm1,#0 1 00_ 11 00b;16bit mode ldm tdr0,#<62500 ;8us x 62500 ldm tdr1,#>62500 ;=0.5s set1 t0e ei : : example 2: timer0 = 16-bit event counter mode ldm r0func,#0000_0 1 00b;ec0 set ldm tm0,#000 1 _ 11 11b;counter mode ldm tm1,#0 1 00_ 11 00b;16bit mode ldm tdr0,#<0ffh ; ldm tdr1,#>0ffh ; set1 t0e ei : : example 3: timer0 = 16-bit capture mode ldm r0func,#0000_000 1 b;int0 set ldm tm0,#00 1 0_1111b;capture mode ldm tm1,#0 1 00_ 11 00b;16bit mode ldm tdr0,#<0ffh ; ldm tdr1,#>0ffh ; ldm ieds,#01h;falling edge set1 t0e ei : : 12.6 pwm mode the gms81c2120 has a high speed pwm (pulse width modulation) functions which shared with timer1. in pwm mode, pin r56/pwm1o/t1o outputs up to a 10- bit resolution pwm output. this pin should be configured as a pwm output by setting "1" bit pwm1o in r5func.6 register. the period of the pwm output is determined by the t1ppr (pwm1 period register) and pwm1hr[3:2] (bit3,2 of pwm1 high register) and the duty of the pwm output is determined by the t1pdr (pwm1 duty regis- ter) and pwm1hr[1:0] (bit1,0 of pwm1 high register). the user writes the lower 8-bit period value to the t1ppr and the higher 2-bit period value to the pwm1hr[3:2]. and writes duty value to the t1pdr and the pwm1hr[1:0] same way. the t1pdr is configured as a double buffering for glitch- less pwm output. in figure 12-12, the duty data is trans- ferred from the master to the slave when the period data matched to the counted value. (i.e. at the beginning of next duty cycle) pwm period = [pwm1hr[3:2]t1ppr] x source clock pwm duty = [pwm1hr[1:0]t1pdr] x source clock the relation of frequency and resolution is in inverse pro- portion. table 12-2 shows the relation of pwm frequency vs. resolution.
GMS81C2112/gms81c2120 54 june. 2001 ver 1.00 if it needed more higher frequency of pwm, it should be reduced resolution. the bit pol of tm1 decides the polarity of duty cycle. if the duty value is set same to the period value, the pwm output is determined by the bit pol (1: high, 0: low). and if the duty value is set to "00 h ", the pwm output is deter- mined by the bit pol (1: low, 0: high). it can be changed duty value when the pwm output. how- ever the changed duty value is output after the current pe- riod is over. and it can be maintained the duty value at present output when changed only period value shown as figure 12-14. as it were, the absolute duty time is not changed in varying frequency. but the changed period val- ue must greater than the duty value. figure 12-12 pwm mode resolution frequency t1ck[1:0] = 00(250ns) t1ck[1:0] = 01(500ns) t1ck[1:0] = 10(2us) 10-bit 3.9khz 0.98khz 0.49khz 9-bit 7.8khz 1.95khz 0.97khz 8-bit 15.6khz 3.90khz 1.95khz 7-bit 31.2khz 7.81khz 3.90khz table 12-2 pwm frequency vs. resolution at 4mhz ? 1 ? 2 ? 8 pwm1hr address : d5h reset value : ----0000 - - - - pwm1hr3 pwm1hr2 pwm1hr1 pwm1hr0 ---- xxxx mux 1 t1cn t1ck[1:0] t1 ( 8-bit ) t1st 0 : stop 1 : clear and start clear comparator comparator t1pdr(8-bit) pwm1hr[1:0] t1ppr(8-bit) pwm1hr[3:2] t1pdr(8-bit) sq r pol pwm1o r56/ pwm1o/t1o t0 clock source f xi tm1 address : d2h reset value : 00000000 pol 16bit pwm1e cap1 t1ck1 t1ck0 t1cn t1st x010 xxxx [r5func.6] period high duty high slave master bit manipulation not available x : the value "0" or "1" corresponding your operation. [t0ck] (2-bit)
GMS81C2112/gms81c2120 june. 2001 ver 1.00 55 figure 12-13 example of pwm at 4mhz figure 12-14 example of changing the period in absolute duty cycle (@4mhz) source t1 pwm1o ~ ~ ~ ~ ~ ~ 02 03 04 05 7f 80 81 02 03 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ [pol=1] pwm1o [pol=0] duty cycle [ 80h x 250ns = 32us ] period cycle [ 3ffh x 250ns = 255.75us, 3.9khz ] pwm1hr = 0ch t1ppr = ffh t1pdr = 80h t1ck[1:0] = 00 ( f xi ) pwm1hr3 pwm1hr2 pwm1hr1 pwm1hr0 t1ppr (8-bit) t1pdr (8-bit) period duty 11 ffh 00 80h 01 00 clock pwm1e ~ ~ t1st ~ ~ t1cn ~ ~ 01 00 3ff source t1 pwm1o pol=1 duty cycle period cycle [ 0eh x 2us = 28us, 35.5khz ] pwm1hr = 00h t1ppr = 0eh t1pdr = 05h t1ck[1:0] = 10 ( 1us ) 02 03 04 05 06 08 09 0b 0c 0d 0e 01 02 03 04 05 06 07 08 09 0a 01 02 03 04 07 0a 05 [ 05h x 2us = 10us ] duty cycle [ 05h x 2us = 10us ] period cycle [ 0ah x 2us = 20us, 50khz ] duty cycle [ 05h x 2us = 10us ] write t1ppr to 0ah period changed clock 01
GMS81C2112/gms81c2120 56 june. 2001 ver 1.00 13. analog digital converter the analog-to-digital converter (a/d) allows conversion of an analog input signal to a corresponding 8-bit digital value. the a/d module has eight analog inputs, which are multiplexed into one sample and hold. the output of the sample and hold is the input into the converter, which gen- erates the result via successive approximation. the analog supply voltage is connected to av dd of ladder resistance of a/d module. the a/d module has two registers which are the control register adcm and a/d result register adr. the register adcm, shown in figure 13-1, controls the operation of the a/d converter module. the port pins can be configured as analog inputs or digital i/o. to use analog inputs, each port is assigned analog input port by setting the bit ansel[7:0] in r6func register. and selected the corresponding channel to be converted by setting ads[3:0]. how to use a/d converter the processing of conversion is start when the start bit adst is set to "1". after one cycle, it is cleared by hard- ware. the register adcr contains the results of the a/d conversion. when the conversion is completed, the result is loaded into the adcr, the a/d conversion status bit adsf is set to "1", and the a/d interrupt flag adif is set. the block diagram of the a/d module is shown in figure 13-2. the a/d status bit adsf is set automatically when a/d conversion is completed, cleared when a/d conver- sion is in process. the conversion time takes maximum 20 us (at f xi =4 mhz) figure 13-1 a/d converter control register btcl 76543210 - adst a/d status bit analog input channel select initial value: -0-0 0001 b address: 0ea h adcm adsf a/d converter enable bit 0: a/d converter module turn off and current is not flow. 1: enable a/d converter r/w r/w r/w r/w r/w r 000: channel 0 (an0) 001: channel 1 (an1) 010: channel 2 (an2) 011: channel 3 (an3) 100: channel 4 (an4) 101: channel 5 (an5) 110: channel 6 (an6) 111: channel 7 (an7) 0: a/d conversion is in progress 1: a/d conversion is completed a/d start bit setting this bit starts an a/d conversion. after one cycle, bit is cleared to 0 by hardware. ads1 ads0 - ads2 initial value: undefined address: 0eb h adcr a/d conversion data btcl 76543210 rrrr rr r r aden
GMS81C2112/gms81c2120 june. 2001 ver 1.00 57 . figure 13-2 a/d block diagram r60/an0 s/h sample & hold 0 1 aden av dd adif a/d interrupt successive approximation circuit adr (8-bit) a/d result register address: e9 h reset value: undefined 000 ads[2:0] ladder resistor 8-bit dac r61/an1 001 r62/an2 010 r63/an3 011 r64/an4 100 r65/an5 101 r66/an6 110 r67/an7 111 ansel0 r6func[7:0] ansel1 ansel2 ansel3 ansel4 ansel5 ansel6 ansel7
GMS81C2112/gms81c2120 58 june. 2001 ver 1.00 figure 13-3 a/d converter operation flow a/d converter cautions (1) input range of an7 to an0 the input voltage of an7 to an0 should be within the specification range. in particular, if a voltage above a vdd or below avss is input (even if within the absolute maximum rating range), the conversion value for that channel can not be in- determinate. the conversion values of the other channels may also be affected. (2) noise countermeasures in order to maintain 8-bit resolution, attention must be paid to noise on pins avdd and an7 to an0. since the effect increas- es in proportion to the output impedance of the analog in- put source, it is recommended that a capacitor be connected externally as shown in figure 13-4 in order to reduce noise. figure 13-4 analog input pin connecting capacitor (3) pins an7/r67 to an0/r60 the analog input pins an7 to an0 also function as input/ output port (port r6) pins. when a/d conversion is per- formed with any of pins an7 to an0 selected, be sure not to execute a port input instruction while conversion is in progress, as this may reduce the conversion resolution. also, if digital pulses are applied to a pin adjacent to the pin in the process of a/d conversion, the expected a/d conversion value may not be obtainable due to coupling noise. therefore, avoid applying pulses to pins adjacent to the pin undergoing a/d conversion. (4) avdd pin input impedance a series resistor string of approximately 10k w is connected be- tween the avdd pin and the avss pin. therefore, if the output impedance of the reference voltage source is high, this will result in parallel connection to the series resistor string between the avdd pin and the avss pin, and there will be a large reference voltage error. enable a/d converter a/d start ( adst = 1 ) nop adsf = 1 a/d input channel select analog reference select read adcr yes no an11~an0 100~1000pf analog input
GMS81C2112/gms81c2120 june. 2001 ver 1.00 59 14. serial peripheral interface the serial peripheral interface (spi) module is a serial in- terface useful for communicating with other peripheral of microcontroller devices. these peripheral devices may be serial eeproms, shift registers, display drivers, a/d con- verters, etc. the serial peripheral interface(spi) is 8-bit clock synchronous type and consists of serial i/o register, serial i/o mode register, clock selection circuit octal counter and control circuit. the sout pin is designed to input and output. so serial peripheral interface(spi) can be operated with minimum two pin figure 14-1 spi block diagram ? 4 ? 16 xin pin prescaler mux sck[1:0] 00 01 10 11 sclk pin spi shift input shift register sior clock clock octal serial communication interrupt sioif sout internal bus siosf counter sck[1:0] 11 overflow not 11 complete timer0 overflow ioswin sin pin iosw pin sout ioswin control circuit 0 1 pol 1 0 start siost
GMS81C2112/gms81c2120 60 june. 2001 ver 1.00 serial i/o mode register(siom) controls serial i/o func- tion. according to sck1 and sck0, the internal clock or external clock can be selected. the serial transmission op- eration mode is decided by setting the sm1 and sm0, and the polarity of transfer clock is selected by setting the pol. serial i/o data register(sior) is a 8-bit shift register. first lsb is send or is received. when receiving mode, se- rial input pin is selected by iosw. the spi allows 8-bits of data to be synchronously transmitted and received. to accomplish communication, typically three pins are used: - serial data in r54/sin - serial data out r55/sout - serial clock r53/sclk . figure 14-2 spi control register btcl 76543210 iosw pol siost serial transmission status bit serial transmission clock selection initial value: 0000 0001 b address: 0e0 h siom siosf serial input pin selection bit 0: sin pin selection 1: ioswin pin selection r/w r/w r/w r/w r/w r 00: f xin ? 4 01: f xin ? 16 10: tmr0ov(timer0 overflow) 11: external clock 0: serial transmission is in progress 1: serial transmission is completed serial transmission start bit setting this bit starts an serial transmission. after one cycle, bit is cleared to 0 by hardware. sck1 sck0 sm1 sm0 r/w serial transmission operation mode 00: normal port(r55,r54,r53) 01: sending mode(sout,r54,sclk) 10: receiving mode(r55,sin,sclk) 11: sending & receiving mode(sout,sin,sclk) initial value: undefined address: 0e1 h sior btcl 76543210 r/w r/w r/w r/w r/w r/w r/w r/w sending data at sending mode receiving data at receiving mode serial clock polarity selection bit 0: data transmission at falling edge received data latch at rising edge 1: data transmission at rising edge received data latch at falling edge r/w
GMS81C2112/gms81c2120 june. 2001 ver 1.00 61 14.1 transmission/receiving timing the serial transmission is started by setting siost(bit1 of siom) to 1. after one cycle of sck, siost is cleared automatically to 0. the serial output data from 8-bit shift register is output at falling edge of sclk. and input data is latched at rising edge of sclk pin. when transmission clock is counted 8 times, serial i/o counter is cleared as 0. transmission clock is halted in h state and serial i/ o interrupt(ifsio) occurred. figure 14-3 spi timing diagram at pol=0 figure 14-4 spi timing diagram at pol=1 d1 d2 d3 d4 d6 d7 d0 d5 d1 d2 d3 d4 d6 d7 d0 d5 siost sclk [r53] (pol=0) sout [r55] sin [r54] spiif (spi int. req) (iosw=0) d1 d2 d3 d4 d6 d7 d0 d5 ioswin [r55] (iosw=1) siosf (spi status) d1 d2 d3 d4 d6 d7 d0 d5 d1 d2 d3 d4 d6 d7 d0 d5 siost sclk [r53] (pol=1) sout [r55] sin [r54] spiif (spi int. req) (iosw=0) d1 d2 d3 d4 d6 d7 d0 d5 ioswin [r55] (iosw=1) siosf (spi status)
GMS81C2112/gms81c2120 62 june. 2001 ver 1.00 14.2 the method of serial i/o select transmission/receiving mode note: when external clock is used, the frequency should be less than 1mhz and recommended duty is 50%. in case of sending mode, write data to be send to sior. set siost to 1 to start serial transmission. note: if both transmission mode is selected and transmis- sion is performed simultaneously it would be made error. the sio interrupt is generated at the completion of sio and siosf is set to 1. in sio interrupt service routine, correct transmission should be tested.
in case of receiving mode, the received data is acquired by reading the sior. 14.3 the method to test correct transmission figure 14-5 serial method to test transmission serial i/o interrupt service routine se = 0 write siom normal operation overrun error abnormal siosf 0 1 - se : interrupt enable register low ienl(bit3) - sr : interrupt request flag register low irql(bit3) sr 0 1
GMS81C2112/gms81c2120 june. 2001 ver 1.00 63 15. buzzer function the buzzer driver block consists of 6-bit binary counter, buzzer register bur, and clock source selector. it gener- ates square-wave which has very wide range frequency (480hz ~ 250khz at f xin = 4mhz) by user software. a 50% duty pulse can be output to r03/buzo pin to use for piezo-electric buzzer drive . pin r03 is assigned for output port of buzzer driver by setting the bit 3 of r0func(address 0f4 h ) to 1. at this time, the pin r03 must be defined as output mode (the bit 3 of r0io=1). example: 5khz output at 4mhz. ldm r0io,#xxxx_1xxxb ldm bur,#0011_0010b ldm r0func,#xxxx_1xxxb x means dont care the bit 0 to 5 of bur determines output frequency for buzzer driving. equation of frequency calculation is shown below. f buz : buzzer frequency f xin : oscillator frequency divide ratio: prescaler divide ratio by buck[1:0] bur: lower 6-bit value of bur. buzzer period value. the frequency of output signal is controlled by the buzzer control register bur.the bit 0 to bit 5 of bur determine output frequency for buzzer driving. figure 15-1 block diagram of buzzer driver figure 15-2 r0func and buzzer register f buz f xin 2 divideratio bur 1 + () --------------------------------------------------------------------------- - = prescaler ? 8 ? 32 ? 16 ? 64 bur r03/buzo pin r0func internal bus line r03 port data xin pin 6-bit binary 2 6 [0de h ] [0f4 h ] 0 1 f/f ? 2 comparator compare data 6-bit counter mux 00 01 10 11 port selection 3 bur[5:0] bur address: 0de h reset value: undefined wwwwww source clock select 00: ? 8 01: ? 16 10: ? 32 11: ? 64 buzzer period data r03/buzo selection r0func address : 0f4 h reset value : ---- 0000 b w - - 0: r03 port (turn off buzzer) 1: buzo port (turn on buzzer) ww w buck1 buck0 ww - - buzo ec0 int1 int0
GMS81C2112/gms81c2120 64 june. 2001 ver 1.00 note: bur is undefined after reset, so it must be initialized to between 1 h and 3f h by software. note that bur is a write-only register. the 6-bit counter is cleared and starts the counting by writ- ing signal at bur register. it is incremental from 00 h until it matches 6-bit bur value. when main-frequency is 4mhz, buzzer frequency is shown as below table. bur [5:0] bur[7:6] bur [5:0] bur[7:6] 00 01 10 11 00 01 10 11 00 01 02 03 04 05 06 07 250.000 125.000 83.333 62.500 50.000 41.667 35.714 31.250 125.000 62.500 41.667 31.250 25.000 20.833 17.857 15.625 62.500 31.250 20.833 15.625 12.500 10.417 8.929 7.813 31.250 15.625 10.417 7.813 6.250 5.208 4.464 3.906 20 21 22 23 24 25 26 27 7.576 7.353 7.143 6.944 6.757 6.579 6.410 6.250 3.788 3.676 3.571 3.472 3.378 3.289 3.205 3.125 1.894 1.838 1.786 1.736 1.689 1.645 1.603 1.563 0.947 0.919 0.893 0.868 0.845 0.822 0.801 0.781 08 09 0a 0b 0c 0d 0e 0f 27.778 25.000 22.727 20.833 19.231 17.857 16.667 15.625 13.889 12.500 11.364 10.417 9.615 8.929 8.333 7.813 6.944 6.250 5.682 5.208 4.808 4.464 4.167 3.906 3.472 3.125 2.841 2.604 2.404 2.232 2.083 1.953 28 29 2a 2b 2c 2d 2e 2f 6.098 5.952 5.814 5.682 5.556 5.435 5.319 5.208 3.049 2.976 2.907 2.841 2.778 2.717 2.660 2.604 1.524 1.488 1.453 1.420 1.389 1.359 1.330 1.302 0.762 0.744 0.727 0.710 0.694 0.679 0.665 0.651 10 11 12 13 14 15 16 17 14.706 13.889 13.158 12.500 11.905 11.364 10.870 10.417 7.353 6.944 6.579 6.250 5.952 5.682 5.435 5.208 3.676 3.472 3.289 3.125 2.976 2.841 2.717 2.604 1.838 1.736 1.645 1.563 1.488 1.420 1.359 1.302 30 31 32 33 34 35 36 37 5.102 5.000 4.902 4.808 4.717 4.630 4.545 4.464 2.551 2.500 2.451 2.404 2.358 2.315 2.273 2.232 1.276 1.250 1.225 1.202 1.179 1.157 1.136 1.116 0.638 0.625 0.613 0.601 0.590 0.579 0.568 0.558 18 19 1a 1b 1c 1d 1e 1f 10.000 9.615 9.259 8.929 8.621 8.333 8.065 7.813 5.000 4.808 4.630 4.464 4.310 4.167 4.032 3.906 2.500 2.404 2.315 2.232 2.155 2.083 2.016 1.953 1.250 1.202 1.157 1.116 1.078 1.042 1.008 0.977 38 39 3a 3b 3c 3d 3e 3f 4.386 4.310 4.237 4.167 4.098 4.032 3.968 3.907 2.193 2.155 2.119 2.083 2.049 2.016 1.984 1.953 1.096 1.078 1.059 1.042 1.025 1.008 0.992 0.977 0.548 0.539 0.530 0.521 0.512 0.504 0.496 0.488
GMS81C2112/gms81c2120 june. 2001 ver 1.00 65 16. interrupts the gms81c21xx interrupt circuits consist of interrupt enable register (ienh, ienl), interrupt request flags of irqh, irql, priority circuit, and master enable flag (i flag of psw). nine interrupt sources are provided. the configuration of interrupt circuit is shown in figure 16-2. the external interrupts int0 and int1 each can be transi- tion-activated (1-to-0 or 0-to-1 transition) by selection ieds. the flags that actually generate these interrupts are bit int0f and int1f in register irqh. when an external in- terrupt is generated, the flag that generated it is cleared by the hardware when the service routine is vectored to only if the interrupt was transition-activated. the timer 0 ~ timer 1 interrupts are generated by txif which is set by a match in their respective timer/counter register. the basic interval timer interrupt is generated by bitif which is set by an overflow in the timer register. the ad converter interrupt is generated by adif which is set by finishing the analog to digital conversion. the watchdog timer interrupt is generated by wdtif which set by a match in watchdog timer register. the basic interval timer interrupt is generated by bitif which are set by a overflow in the timer counter register. the interrupts are controlled by the interrupt master enable flag i-flag (bit 2 of psw on page 21), the interrupt enable register (ienh, ienl), and the interrupt request flags (in irqh and irql) except power-on reset and software brk interrupt. below table shows the interrupt priority. vector addresses are shown in figure 8-6 on page 23. in- terrupt enable registers are shown in figure 16-3. these registers are composed of interrupt enable flags of each in- terrupt source and these flags determines whether an inter- rupt will be accepted or not. when enable flag is 0, a corresponding interrupt source is prohibited. note that psw contains also a master enable bit, i-flag, which dis- ables all interrupts at once. figure 16-1 interrupt request flag reset/interrupt symbol priority hardware reset external interrupt 0 external interrupt 1 timer/counter 0 timer/counter 1 - - - - adc interrupt watchdog timer basic interval timer serial communication reset int0 int1 timer0 timer1 - - - - adc wdt bit sci - 1 2 3 4 - - - - 5 6 7 8 r/w int0if initial value: 0000 ---- b address: 0e4 h irqh int1if msb t0if t1if r/w timer/counter 1 interrupt request flag spif r/w adif serial communication interrupt request flag initial value: 0000 ---- b address: 0e5 h irql wdtif msb lsb - - - bitif r/w timer/counter 0 interrupt request flag - r/w r/w r/w r/w - - -- basic interval imer interrupt request flag watchdog timer interrupt request flag a/d conver interrupt request flag external interrupt 1 request flag external interrupt 0 request flag lsb - - -- - - --
GMS81C2112/gms81c2120 66 june. 2001 ver 1.00 . figure 16-2 block diagram of interrupt figure 16-3 interrupt enable flag timer 0 int1 int0 int0if ienh interrupt enable interrupt enable irqh irql interrupt vector address generator internal bus line register (lower byte) internal bus line register (higher byte) release stop to cpu interrupt master enable flag i-flag ienl priority control i-flag is in psw, it is cleared by "di", set by "ei" instruction. when it goes interrupt service, i-flag is cleared by hardware, thus any other interrupt are inhibited. when interrupt service is completed by "reti" instruction, i-flag is set to "1" by hardware. [0e2 h ] [0e3 h ] [0e4 h ] [0e5 h ] int1if t0if timer 1 t1if a/d converter adif sioif bitif watchdog timer serial bit wdtif communication t1e r/w int0e initial value: 0000 ---- b address: 0e2 h ienh int1e msb t0e r/w timer/counter 1 interrupt enable flag spie r/w ade serial communication interrupt enable flag initial value: 0000 ---- b address: 0e3 h ienl wdte msb lsb - - - bite r/w timer/counter 0 interrupt enable flag - r/w r/w r/w r/w - - -- basic interval imer interrupt enable flag watchdog timer interrupt enable flag a/d convert interrupt enable flag external interrupt 1 enable flag external interrupt 0 enable flag 0: disable 1: enable value lsb - - -- - - --
GMS81C2112/gms81c2120 june. 2001 ver 1.00 67 16.1 interrupt sequence an interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to 0 by a reset or an in- struction. interrupt acceptance sequence requires 8 f xin (2 m s at f main =4.19mhz) after the completion of the current instruction execution. the interrupt service task is termi- nated upon execution of an interrupt return instruction [reti]. interrupt acceptance 1. the interrupt master enable flag (i-flag) is cleared to 0 to temporarily disable the acceptance of any follow- ing maskable interrupts. when a non-maskable inter- rupt is accepted, the acceptance of any following interrupts is temporarily disabled. 2. interrupt request flag for the interrupt source accepted is cleared to 0. 3. the contents of the program counter (return address) and the program status word are saved (pushed) onto the stack area. the stack pointer decreases 3 times. 4. the entry address of the interrupt service program is read from the vector table address and the entry address is loaded to the program counter. 5. the instruction stored at the entry address of the inter- rupt service program is executed. figure 16-4 timing chart of interrupt acceptance and interrupt return instruction a interrupt request is not accepted until the i-flag is set to 1 even if a requested interrupt has higher priority than that of the current interrupt being serviced. when nested interrupt service is required, the i-flag should be set to 1 by ei instruction in the interrupt service program. in this case, acceptable interrupt sources are se- lectively enabled by the individual interrupt enable flags. saving/restoring general-purpose register during interrupt acceptance processing, the program counter and the program status word are automatically saved on the stack, but accumulator and other registers are not saved itself. these registers are saved by the software if necessary. also, when multiple interrupt services are nested, it is necessary to avoid using the same data memory v.l. system clock address bus pc sp sp-1 sp-2 v.h. new pc v.l. data bus not used pch pcl psw adl op code adh instruction fetch internal read internal write interrupt processing step interrupt service task v.l. and v.h. are vector addresses. adl and adh are start addresses of interrupt service routine as vector contents. basic interval timer 012 h 0e3 h 0ffe6 h 0ffe7 h 0e h 2e h 0e312 h 0e313 h entry address correspondence between vector table address for bit interrupt and the entry address of the interrupt service program. vector table address
GMS81C2112/gms81c2120 68 june. 2001 ver 1.00 area for saving registers. the following method is used to save/restore the general- purpose registers. example: register save using push and pop instructions general-purpose register save/restore using push and pop instructions; 16.2 brk interrupt software interrupt can be invoked by brk instruction, which has the lowest priority order. interrupt vector address of brk is shared with the vector of tcall 0 (refer to program memory section). when brk interrupt is generated, b-flag of psw is set to distin- guish brk from tcall 0. each processing step is determined by b-flag as shown in figure 16-5. figure 16-5 execution of brk/tcall0 intxx: push a push x push y ;save acc. ;save x reg. ;save y reg. interrupt processing pop y pop x pop a reti ;restore y reg. ;restore x reg. ;restore acc. ;return main task interrupt service task saving registers restoring registers acceptance of interrupt interrupt return b-flag brk interrupt routine reti tcall0 routine ret brk or tcall0 =0 =1
GMS81C2112/gms81c2120 june. 2001 ver 1.00 69 16.3 multi interrupt if two requests of different priority levels are received si- multaneously, the request of higher priority level is ser- viced. if requests of the interrupt are received at the same time simultaneously, an internal polling sequence deter- mines by hardware which request is serviced. figure 16-6 execution of multi interrupt however, multiple processing through software for special features is possible. generally when an interrupt is accept- ed, the i-flag is cleared to disable any further interrupt. but as user sets i-flag in interrupt routine, some further inter- rupt can be serviced even if certain interrupt is in progress. example: during timer1 interrupt is in progress, int0 in- terrupt serviced without any suspend. timer1: push a push x push y ldm ienh,#80h ; enable int0 only ldm ienl,#0 ; disable other ei ; enable interrupt : : : : : : ldm ienh,#0f0h ; enable all interrupts ldm ienl,#0f0h pop y pop x pop a reti enable int0 timer 1 service int0 service main program service occur timer1 interrupt occur int0 ei disable other enable int0 enable other in this example, the int0 interrupt can be serviced without any pending, even timer1 is in progress. because of re-setting the interrupt enable registers ienh,ienl and master enable "ei" in the timer1 routine.
GMS81C2112/gms81c2120 70 june. 2001 ver 1.00 16.4 external interrupt the external interrupt on int0 and int1 pins are edge triggered depending on the edge selection register ieds (address 0f8 h ) as shown in figure 16-7. the edge detection of external interrupt has three transition activated mode: rising edge, falling edge, and both edge. figure 16-7 external interrupt block diagram int0 and int1 are multiplexed with general i/o ports (r00 and r01). to use as an external interrupt pin, the bit of r4 port mode register r0func should be set to 1 cor- respondingly. example: to use as an int0 and int1 : : ; **** set port as an input port r00,r01 ldm r0io,#1111_1100b ; ; **** set port as an interrupt port ldm r0func,#0000_0011b ; ; **** set falling-edge detection ldm ieds,#0000_0101b : : : response time the int0 and int1 edge are latched into int0if and int1if at every machine cycle. the values are not actually polled by the circuitry until the next machine cycle. if a re- quest is active and conditions are right for it to be acknowl- edged, a hardware subroutine call to the requested service routine will be the next instruction to be executed. the div itself takes twelve cycles. thus, a minimum of twelve complete machine cycles elapse between activation of an external interrupt request and the beginning of execution of the first instruction of the service routine. figure 16-8shows interrupt response timings. figure 16-8 interrupt response timing diagram int1if int1 pin int1 interrupt ieds [0e6h] int0if int0 pin int0 interrupt edge selection register 2 2 interrupt goes active interrupt latched interrupt processing interrupt routine 8 f xin max. 12 f xin
GMS81C2112/gms81c2120 june. 2001 ver 1.00 71 figure 16-9 r0func and ieds registers btcl wwwwwwww - - - int1 0: r00 1: int0 initial value: ---- 0000 b address: 0f4 h r0func - int0 ec0 buzo 0: r01 1: int1 0: r02 1: ec0 0: r03 1: buzo lsb msb btcl r/w r/w r/w r/w - - -ied0h initial value: ---- 0000 b address: 0e6 h ieds -ied0l ied1l ied1h lsb msb edge selection register 00: reserved 01: falling (1-to-0 transition) 10: rising (0-to-1 transition) 11: both (rising & falling) int0 int1
GMS81C2112/gms81c2120 72 june. 2001 ver 1.00 17. power saving mode for applications where power consumption is a critical factor, device provides four kinds of power saving func- tions, stop mode, sub-active mode and wake-up timer mode (stand-by mode, watch mode). table 17-1 shows the status of each power saving mode. the power saving function is activated by execution of stop instruction and by execution of stop instruction af- ter setting the corresponding status (wakeup) of ckctlr. we shows the release sources from each power saving mode peripheral stop mode wake-up timer mode stand-by mode ram retain retain control registers retain retain i/o ports retain retain cpu stop stop timer0 stop operation oscillation stop oscillation prescaler stop ? 2048 only entering condition [wakeup] 01 table 17-1 power saving mode release source stop mode wake-up timer mode stand-by mode reset o o rcwdt o o ext.int0 oo ext.int1 timer0 x o table 17-2 release sources from power saving mode
GMS81C2112/gms81c2120 june. 2001 ver 1.00 73 17.1 operating mode active mode f xi : oscillation cpu : f sys tmr : f sys peri : f sys standby mode f xi : oscillation cpu : stop tmr : ps11(f xi ) peri : stop ckctlr[10] + stop timer0 ext_int reset rc_wdt stop mode f xi : stop cpu : stop tmr : stop peri : stop ext_int reset rc_wdt ckctlr[00] + stop system clock mode register scmr address : fah reset value : ---00--- - - - cs1 cs0 - - - cs[1:0] clock selection enable bits 00 : f xi 10 : f xi ? 8 01 : f xi ? 4 11 : f xi ? 32 f sys : f xi ,f xi ?4 ,f xi ? 8,f xi ? 32 cpu : system clock tmr : timer0 clock peri : peripheral clock ckctlr = ckctlr[6:5] f xi : main clock frequency
GMS81C2112/gms81c2120 74 june. 2001 ver 1.00 17.2 stop mode in the stop mode, the on-chip oscillator is stopped. with the clock frozen, all functions are stopped, but the on-chip ram and control registers are held. the port pins out the values held by their respective port data register, port di- rection registers. oscillator stops and the systems internal operations are all held up. ? the states of the ram, registers, and latches valid immediately before the system is put in the stop state are all held. ? the program counter stop the address of the instruction to be executed after the instruction "stop" which starts the stop operating mode. the stop mode is activated by execution of stop in- struction after clearing the bit wakeup of ckctlr to 0. (this register should be written by byte opera- tion. if this register is set by bit manipulation instruc- tion, for example "set1" or "clr1" instruction, it may be undesired operation) in the stop mode of operation, v dd can be reduced to min- imize power consumption. care must be taken, however, to ensure that v dd is not reduced before the stop mode is invoked, and that v dd is restored to its normal operating level, before the stop mode is terminated. the reset should not be activated before v dd is restored to its normal operating level, and must be held active long enough to allow the oscillator to restart and stabilize. note: after stop instruction, at least two or more nop in- struction should be written ex) ldm ckctlr,#0000_1110b stop nop nop in the stop operation, the dissipation of the power asso- ciated with the oscillator and the internal hardware is low- ered; however, the power dissipation associated with the pin interface (depending on the external circuitry and pro- gram) is not directly determined by the hardware operation of the stop feature. this point should be little current flows when the input level is stable at the power voltage level (v dd /v ss ); however, when the input level gets high- er than the power voltage level (by approximately 0.3 to 0.5v), a current begins to flow. therefore, if cutting off the output transistor at an i/o port puts the pin signal into the high-impedance state, a current flow across the ports input transistor, requiring to fix the level by pull-up or other means. release the stop mode the exit from stop mode is hardware reset or external in- terrupt. reset re-defines all the control registers but does not change the on-chip ram. external interrupts allow both on-chip ram and control registers to retain their val- ues. if i-flag = 1, the normal interrupt response takes place. if i- flag = 0, the chip will resume execution starting with the instruction following the stop instruction. it will not vec- tor to interrupt service routine. (refer to figure 17-1) when exit from stop mode by external interrupt, enough oscillation stabilization time is required to normal opera- tion. figure 17-2 shows the timing diagram. when release the stop mode, the basic interval timer is activated on wake-up. it is increased from 00 h until ff h . the count overflow is set to start normal operation. therefore, before stop instruction, user must be set its relevant prescaler di- vide ratio to have long enough time (more than 20msec). this guarantees that oscillator has started and stabilized. by reset, exit from stop mode is shown in figure . figure 17-1 stop releasing flow by interrupts iexx =0 =1 stop instruction stop mode interrupt request stop mode release i-flag =1 interrupt service routine next instruction =0 master interrupt enable bit psw[2] corresponding interrupt enable bit (ienh, ienl)
GMS81C2112/gms81c2120 june. 2001 ver 1.00 75 . figure 17-2 stop mode release timing by external interrupt figure 17-3 timing of stop mode release by reset 17.3 wake-up timer mode in the wake-up timer mode, the on-chip oscillator is not stopped. except the prescaler(only 2048 divided ratio) and timer0, all functions are stopped, but the on-chip ram and control registers are held. the port pins out the values held by their respective port data register, port direction registers. the wake-up timer mode is activated by execution of stop instruction after setting the bit wakeup of ckctlr to 1. (this register should be written by byte operation. if this register is set by bit manipulation instruction, for example "set1" or "clr1" instruction, it may be undesired operation) note: after stop instruction, at least two or more nop in- struction should be written ex) ldm tdr0,#0ffh ldm tm0,#0001_1011b ldm ckctlr,#0100_1110b stop nop nop in addition, the clock source of timer0 should be selected to 2048 divided ratio. otherwise, the wake-up function can not work. and the timer0 can be operated as 16-bit timer with timer1. (refer to timer function)the period of wake- up function is varied by setting the timer data register 0, tdr0. before executing stop instruction, basic interval timer must be set oscillator (x in pin) ~ ~ n 0 bit counter n+1 n+2 n+3 ~ ~ normal operation stop operation normal operation 1 fe ff 0 12 ~ ~ ~ ~ ~ ~ t st > 20ms ~ ~ ~ ~ external interrupt internal clock clear stop instruction executed ~ ~ ~ ~ ~ ~ properly by software to get stabilization time which is longer than 20ms. by software ~ ~ ~ ~ stop mode time can not be control by software oscillator (xi pin) ~ ~ ~ ~ ~ ~ stop instruction execution stabilization time t st = 64ms @4mhz internal clock internal ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ resetb resetb
GMS81C2112/gms81c2120 76 june. 2001 ver 1.00 release the wake-up timer mode the exit from wake-up timer mode is hardware reset, timer0 overflow or external interrupt. reset re-defines all the control registers but does not change the on-chip ram. external interrupts and timer0 overflow allow both on-chip ram and control registers to retain their values. if i-flag = 1, the normal interrupt response takes place. if i- flag = 0, the chip will resume execution starting with the instruction following the stop instruction. it will not vec- tor to interrupt service routine.(refer to figure 17-1) when exit from wake-up timer mode by external inter- rupt or timer0 overflow, the oscillation stabilization time is not required to normal operation. because this mode do not stop the on-chip oscillator shown as figure 17-4. figure 17-4 wake-up timer mode releasing by external interrupt or timer0 interrupt 17.4 internal rc-oscillated watchdog timer mode in the internal rc-oscillated watchdog timer mode, the on-chip oscillator is stopped. but internal rc oscillation circuit is oscillated in this mode. the on-chip ram and control registers are held. the port pins out the values held by their respective port data register, port direction regis- ters. the internal rc-oscillated watchdog timer mode is activated by execution of stop instruction after set- ting the bit wakeup and rcwdt of ckctlr to " 01 ". (this register should be written by byte operation. if this register is set by bit manipulation instruction, for example "set1" or "clr1" instruction, it may be unde- sired operation) note: caution: after stop instruction, at least two or more nop instruction should be written ex) ldm wdtr ,#1111_1111b ldm ckctlr ,#0 01 0_1110b stop nop nop the exit from internal rc-oscillated watchdog timer mode is hardware reset or external interrupt. reset re-de- fines all the control registers but does not change the on- chip ram. external interrupts allow both on-chip ram and control registers to retain their values. if i-flag = 1, the normal interrupt response takes place. in this case, if the bit wdton of ckctlr is set to "0" and the bit wdte of ienh is set to "1", the device will execute the watchdog timer interrupt service routine.(figure 17-5) however, if the bit wdton of ckctlr is set to "1", the device will generate the internal reset signal and exe- cute the reset processing. (figure 17-6) if i-flag = 0, the chip will resume execution starting with the instruction following the stop instruction. it will not vector to interrupt service routine.(refer to figure 17-1) when exit from internal rc-oscillated watchdog timer mode by external interrupt, the oscillation stabilization time is required to normal operation. figure 17-5 shows the timing diagram. when release the internal rc-oscil- lated watchdog timer mode, the basic interval timer is ac- tivated on wake-up. it is increased from 00 h until ff h . the count overflow is set to start normal operation. therefore, before stop instruction, user must be set its relevant pres- caler divide ratio to have long enough time (more than 20msec). this guarantees that oscillator has started and stabilized. by reset, exit from internal rc-oscillated watchdog tim- er mode is shown in figure 17-6. wake-up timer mode oscillator (xi pin) ~ ~ stop instruction normal operation normal operation cpu clock request interrupt ~ ~ ~ ~ execution do not need stabilization time ( stop the cpu clock ) ~ ~
GMS81C2112/gms81c2120 june. 2001 ver 1.00 77 figure 17-5 internal rcwdt mode releasing by external interrupt or wdt interrupt figure 17-6 internal rcwdt mode releasing by reset 17.5 minimizing current consumption the stop mode is designed to reduce power consumption. to minimize current drawn during stop mode, the user should turn-off output drivers that are sourcing or sinking current, if it is practical. note: in the stop operation, the power dissipation asso- ciated with the oscillator and the internal hardware is low- ered; however, the power dissipation associated with the pin interface (depending on the external circuitry and pro- gram) is not directly determined by the hardware operation of the stop feature. this point should be little current flows when the input level is stable at the power voltage level (v dd /v ss ); however, when the input level becomes higher ~ ~ rcwdt mode normal operation oscillator (xi pin) ~ ~ ~ ~ n+1 n n+2 00 01 fe ff 00 00 n-1 n-2 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ clear basic interval timer stop instruction execution normal operation stabilization time t st > 20ms internal clock external interrupt bit counter ~ ~ internal rc clock ( or wdt interrupt ) ~ ~ oscillator (xi pin) ~ ~ ~ ~ ~ ~ ~ ~ internal clock internal rc clock time can not be control by software ~ ~ stop instruction execution stabilization time t st = 64ms @4mhz internal ~ ~ ~ ~ ~ ~ reset by wdt reset reset rcwdt mode
GMS81C2112/gms81c2120 78 june. 2001 ver 1.00 than the power voltage level (by approximately 0.3v), a cur- rent begins to flow. therefore, if cutting off the output tran- sistor at an i/o port puts the pin signal into the high- impedance state, a current flow across the ports input tran- sistor, requiring it to fix the level by pull-up or other means. it should be set properly in order that current flow through port doesn't exist. first conseider the setting to input mode. be sure that there is no current flow after considering its relationship with external circuit. in input mode, the pin impedance viewing from external mcu is very high that the current doesnt flow. but input voltage level should be v ss or v dd . be careful that if unspecified voltage, i.e. if unfirmed voltage level (not v ss or v dd ) is applied to input pin, there can be little current (max. 1ma at around 2v) flow. if it is not appropriate to set as an input mode, then set to output mode considering there is no current flow. setting to high or low is decided considering its relationship with external circuit. for example, if there is external pull-up re- sistor then it is set to output mode, i.e. to high, and if there is external pull-down register, it is set to low. figure 17-7 application example of unused input port figure 17-8 application example of unused output port input pin v dd gnd i v dd x weak pull-up current flows v dd internal pull-up input pin i v dd x very weak current flows v dd o o open open i=0 o i=0 o gnd when port is configured as an input, input level should be closed to 0v or 5v to avoid power consumption. output pin gnd i in the left case, much current flows from port to gnd. x on off output pin gnd i in the left case, tr. base current flows from port to gnd. i=0 x off on v dd l on off open gnd v dd l on off to avoid power consumption, there should be low output on off o o v dd o to the port .
GMS81C2112/gms81c2120 june. 2001 ver 1.00 79 18. oscillator circuit the gms81c21xx has an oscillation circuits internally. x in and x out are input and output for main frequency re- spectively, inverting amplifier which can be configured for being used as an on-chip oscillator, as shown in figure 18- 1. figure 18-1 oscillation circuit oscillation circuit is designed to be used either with a ce- ramic resonator or crystal oscillator. since each crystal and ceramic resonator have their own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. oscillation circuit is designed to be used either with a ce- ramic resonator or crystal oscillator. since each crystal and ceramic resonator have their own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. in addition, see figure 18-2 for the layout of the crystal. note: minimize the wiring length. do not allow the wiring to intersect with other signal conductors. do not allow the wir- ing to come near changing high current. set the potential of the grounding position of the oscillator capacitor to that of v ss . do not ground it to any ground pattern where high cur- rent is present. do not fetch signals from the oscillator. figure 18-2 layout of oscillator pcb circuit x out x in v ss recommend c1,c2 = 20pf c1 c2 x out x in external clock open x out x in external oscillator rc oscillator (mask option) crystal or ceramic oscillator 4.19mhz crystal oscillator ceramic resonator c1,c2 = 30pf refer to ac characteristics for selection r value, r ext x out x in
GMS81C2112/gms81c2120 80 june. 2001 ver 1.00 19. reset the gms81c21xx have two types of reset generation pro- cedures; one is an external reset input, the other is a watch- dog timer reset. table 19-1 shows on-chip hardware ini- tialization by reset action. table 19-1 initializing internal status by reset action 19.1 external reset input the reset input is the reset pin, which is the input to a schmitt trigger. a reset in accomplished by holding the reset pin low for at least 8 oscillator periods, within the operating voltage range and oscillation stable, it is applied, and the internal state is initialized. after reset, 64ms (at 4 mhz) add with 7 oscillator periods are required to start ex- ecution as shown in figure 19-2. internal ram is not affected by reset. when v dd is turned on, the ram content is indeterminate. therefore, this ram should be initialized before read or tested it. when the reset pin input goes to high, the reset opera- tion is released and the program execution starts at the vec- tor address stored at addresses fffe h - ffff h . a connection for simple power-on-reset is shown in figure 19-1. figure 19-1 simple power-on-reset circuit figure 19-2 timing diagram after reset 19.2 watchdog timer reset refer to 11. watchdog timer on page 39. on-chip hardware initial value on-chip hardware initial value program counter (pc) (ffff h ) - (fffe h ) peripheral clock off ram page register (rpr) 0 watchdog timer disable g-flag (g) 0 control registers refer to table 8-1 on page 27 operation mode main-frequency clock power fail detector disable 7036p v cc 10uf + 10k w to the reset pin main program oscillator (x in pin) ? ? fffe ffff stabilization time t st = 62.5ms at 4.19mhz reset address data 1 2 3 4 5 6 7 ?? start ? ? ? fe ? adl adh op bus bus reset process step ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ t st = x 256 f main ? 1024 1
GMS81C2112/gms81c2120 june. 2001 ver 1.00 81 20. power fail processor the gms81c21xx has an on-chip power fail detection cir- cuitry to immunize against power noise. a configuration register, pfdr, can enable or disable the power fail detect circuitry. whenever v dd falls close to or below power fail voltage for 100ns, the power fail situation may reset or freeze mcu according to pfdm bit of pfdr. refer to 7.4 dc electrical characteristics for standard pins(5v) on page 14. in the in-circuit emulator, power fail function is not imple- mented and user can not experiment with it. therefore, af- ter final development of user program, this function may be experimented or evaluated. note: user can select power fail voltage level according to pfd0, pfd1 bit of config register(703f h ) at the otp (gms87c21xx) but must select the power fail voltage level to define pfd option of mask order & verification sheet at the mask chip(gms81c21xx). because the power fail voltage level of mask chip (gms81c21xx) is determined according to mask option. note: if power fail voltage is selected to 3.0v on 3v oper- ation, mcu is freezed at all the times. table 20-1 power fail processor . figure 20-1 power fail voltage detector register power failfunction otp mask enable/disable pfdis flag pfdis flag level selection pfs0 bit pfs1 bit mask option pfdm 76543210 pfs initial value: ---- -100 b address: 0ef h pfdr r/w r/w r/w pfdis operation mode 0 : normal operation regardless of power fail 1 : mcu will be reset by power fail detection disable flag 0: power fail detection enable 1: power fail detection disable power fail status 0: normal operate 1: set to 1 if power fail is detected
GMS81C2112/gms81c2120 82 june. 2001 ver 1.00 figure 20-2 example s/w of reset flow by power fail figure 20-3 power fail processor situations funtion execution initialize ram data pfs =1 no reset vector initialize all ports initialize registers ram clear yes skip the initial routine pfs = 0 internal reset internal reset internal reset v dd v dd v dd v pfd max v pfd min v pfd max v pfd min v pfd max v pfd min 64ms 64ms t <64ms 64ms when pfr = 1
GMS81C2112/gms81c2120 june. 2001 ver 1.00 83 21. otp programming 21.1 device configuration area the device configuration area can be programmed or left unprogrammed to select device configuration such as secu- rity bit. sixteen memory locations (7030 h ~ 703f h ) are designated as customer id recording locations where the user can store check-sum or other customer identification numbers. this area is not accessible during normal execution but is readable and writable during program / verify. figure 21-1 device configuration area device 7030 h 7030 h 703f h 703f h id config configuration area 7031 h id 7032 h id 7033 h id 7034 h id 7035 h id 7036 h id 7037 h id 7038 h id 7039 h id 703a h id 703b h id 703c h id 703d h id 703e h id 76543210 rco initial value: --00 -0-0 b address: 703f h config lock code protect 0 : allow code read out 1 : lock code read out pfd level selection 00: pfd = 2.7v 01: pfd = 2.7v external rc osc selection 0: crystal or resonator oscillator 1: external rc oscillator pfs0 pfs1 10: pfd = 3.0v 11: pfd = 2.4v
GMS81C2112/gms81c2120 84 june. 2001 ver 1.00 figure 21-2 pin assignment t vpp a_d0 a_d1 a_d2 a_d3 eprom enable a_d7 a_d6 a_d5 a_d4 ctl2 ctl1 ctl0 v ss ctl3 r53 r54 r55 r56 r57 reset xi xo v ss av ss r60 r61 r62 r63 r64 r65 r66 r67 av dd ra r34 r33 r32 r31 r30 r27 r26 r25 r24 r23 r22 r21 r20 r05 r04 r03 r02 r01 r00 v dd 42pdip 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 r07 r06 v dd pin no. user mode eprom mode pin name pin name description 2 r53 ctl3 read/write control 3 r54 ctl2 address/data control 4 r55 ctl1 write control 1 5 r56 ctl0 write control 0 7 resetb vpp programming power (0v, 12.75v) 8 xi eprom enable high active, latch address in falling edge 9 xo nc no connection 10 vss vss connect to vss (0v) 12 r60 a_d0 address input data input/output a8 a0 d0 13 r61 a_d1 a9 a1 d1 14 r62 a_d2 a10 a2 d2 15 r63 a_d3 a11 a3 d3 16 r64 a_d4 address input data input/output a12 a4 d4 17 r65 a_d5 a13 a5 d5 18 r66 a_d6 a14 a6 d6 19 r67 a_d7 a15 a7 d7 21 vdd vdd connect to vdd (6.0v) table 21-1 pin description in eprom mode (gms81c2120)
GMS81C2112/gms81c2120 june. 2001 ver 1.00 85 figure 21-3 timing diagram in program (write & verify) mode vpp ctl0/1 ~ ~ high 8bit ha la data in data ~ ~ ~ ~ ~ ~ ~ ~ out la data in data out eprom enable ctl2 ctl3 a_d7~ vdd v dd1h 0v 0v 0v address input low 8bit address input write mode verify low 8bit address input write mode verify a_d0 t vdds t vppr t vpps ~ ~ v dd1h v dd1h v ihp ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ t hld1 t hld2 t set1 t dly1 t dly2 t cd1 t cd1 t cd1 t cd1
GMS81C2112/gms81c2120 86 june. 2001 ver 1.00 figure 21-4 timing diagram in read mode parameter symbol min typ max unit programming supply current i vpp --50ma supply current in eprom mode i vddp --20ma vpp level during programming v ihp 11.5 12.0 12.5 v vdd level in program mode v dd1h 566.5v vdd level in read mode v dd2h -2.7-v ctl3~0 high level in eprom mode v ihc 0.8v dd --v ctl3~0 low level in eprom mode v ilc -- 0.2v dd v a_d7~a_d0 high level in eprom mode v ihad 0.9v dd --v a_d7~a_d0 low level in eprom mode v ilad -- 0.1v dd v vdd saturation time t vdds 1- -ms vpp setup time t vppr --1ms vpp saturation time t vpps 1- -ms eprom enable setup time after data input t set1 200 ns eprom enable hold time after t set1 t hld1 500 ns table 21-2 ac/dc requirements for program/read mode vpp ctl0/1 high 8bit ha la data la data data eprom enable ctl2 ctl3 a_d7~ vdd v dd2h 0v 0v 0v address input low 8bit address input data a_d0 t vdds t vppr t vpps v dd2h v dd2h v ihp t hld1 t hld2 t set1 t dly1 t dly2 t cd1 t cd2 t cd2 t cd1 ha la output low 8bit address input high 8bit address input low 8bit address input data output data output after input a high address, output data following low address input anothe high address step
GMS81C2112/gms81c2120 june. 2001 ver 1.00 87 figure 21-5 programming flow chart eprom enable delay time after t hld1 t dly1 200 ns eprom enable hold time in write mode t hld2 100 ns eprom enable delay time after t hld2 t dly2 200 ns ctl2,1 setup time after low address input and data input t cd1 100 ns ctl1 setup time before data output in read and verify mode t cd2 100 ns table 21-2 ac/dc requirements for program/read mode start set vdd=v dd1h set vpp=v ihp verify blank first address location eprom write n=1 verify last address apply 3x program cycle 100us program time next address location n report programming failure verify of all address vdd=6v & 2.7v report verify failure report programming ok vdd=0v end fail pass pass yes fail no fail yes pass vpp=0v ? verify n=n+1 no
GMS81C2112/gms81c2120 88 june. 2001 ver 1.00
appendix
gms800 series june. 2001 i a. control register list address register name symbol r/w initial value page 76543210 00c0 r0 port data register r0 r/w undefined 34 00c1 r0 port i/o direction register r0io w 0 0 0 0 0 0 0 0 34 00c4 r2 port data register r2 r/w undefined 35 00c5 r2 port i/o direction register r2io w 0 0 0 0 0 0 0 0 35 00c6 r3 port data register r3 r/w undefined 35 00c7 r3 port i/o direction register r3io w - - - 0 0 0 0 0 35 00ca r5 port data register r5 r/w undefined 35 00cb r5 port i/o direction register r5io w 0 0 0 0 0 - - - 35 00cc r6 port data register r6 r/w undefined 35 00cd r6 port i/o direction register r6io w 0 0 0 0 0 0 0 0 35 00d0 timer mode register 0 tm0 r/w - - 000000 44 00d1 timer 0 register t0 r 00000000 48 timer 0 data register tdr0 w 1 1 1 1 1 1 1 1 44 capture 0 data register cdr0 r 0 0 0 0 0 0 0 0 50 00d2 timer mode register 1 tm1 r/w 00000000 44 00d3 timer 1 data register tdr1 w 1 1 1 1 1 1 1 1 44 pwm 1 period register t1ppr w 1 1 1 1 1 1 1 1 54 00d4 timer 1 register t1 r 00000000 48 pwm 1 duty register t1pdr r/w 0 0 0 0 0 0 0 0 54 capture 1 data register cdr1 r 0 0 0 0 0 0 0 0 50 00d5 pwm 1 high register pwm1hr w - - - - 0 0 0 0 54 00de buzzer driver register bur w 1 1 1 1 1 1 1 1 63 00e0 serial i/o mode register siom r/w 0 0 0 0 0 0 0 1 60 00e1 serial i/o data register sior r/w undefined 60 00e2 interrupt enable register high ienh r/w 0 0 0 0 - - - - 66 00e3 interrupt enable register low ienl r/w 0 0 0 0 - - - - 66 00e4 interrupt request flag register high irqh r/w 0 0 0 0 - - - - 65 00e5 interrupt request flag register low irql r/w 0 0 0 0 - - - - 65 00e6 external interrupt edge selection register ieds r/w - - - - 0 0 0 0 71 00ea a/d converter mode register adcm r/w - 0 0 0 0 0 0 1 56 00eb a/d converter data register adcr r undefined 56 00ec basic interval timer mode register bitr r 0 0 0 0 0 0 0 0 38 clock control register ckctlr w - 0 0 1 0 1 1 1 38 00ed watchdog timer register wdtr r 0 0 0 0 0 0 0 0 40 watchdog timer register wdtr w 0 1 1 1 1 1 1 1 40 00ef power fail detection register pfdr r/w - - - - - 1 0 0 81
gms800 series ii june. 2001 00f4 r0 function selection register r0func w - - - - 0 0 0 0 34 00f6 r5 function selection register r5func w - 0 - - - - - - 35 00f7 r6 function selection register r6func w 0 0 0 0 0 0 0 0 35 00f9 r5 n-mos open drain selection register r5mpdr w 0 0 0 0 0 - - - 35 00fa system clock mode register scmr r/w - - - 0 0 - - - 73 00fb ra port data register ra r undefined 34 address register name symbol r/w initial value page 76543210
gms800 series june. 2001 iii b. instruction b.1 terminology list terminology description a accumulator x x - register y y - register psw program status word #imm 8-bit immediate data dp direct page offset address !abs absolute address [ ] indirect expression { } register indirect expression { }+ register indirect expression, after that, register auto-increment .bit bit position a.bit bit position of accumulator dp.bit bit position of direct page memory m.bit bit position of memory data (000 h ~0fff h ) rel relative addressing data upage u-page (0ff00 h ~0ffff h ) offset address n table call number (0~15) + addition x upper nibble expression in opcode y upper nibble expression in opcode - subtraction multiplication / division ( ) contents expression and or ? exclusive or ~not ? assignment / transfer / shift left ? shift right ? exchange = equal 1 not equal 0 bit position 1 bit position
gms800 series iv june. 2001 b.2 instruction map low high 00000 00 00001 01 00010 02 00011 03 00100 04 00101 05 00110 06 00111 07 01000 08 01001 09 01010 0a 01011 0b 01100 0c 01101 0d 01110 0e 01111 0f 000 - set1 dp.bit bbs a.bit,rel bbs dp.bit,rel adc #imm adc dp adc dp+x adc !abs asl a asl dp tcall 0 seta1 .bit bit dp pop a push a brk 001 clrc sbc #imm sbc dp sbc dp+x sbc !abs rol a rol dp tcall 2 clra1 .bit com dp pop x push x bra rel 010 clrg cmp #imm cmp dp cmp dp+x cmp !abs lsr a lsr dp tcall 4 not1 m.bit tst dp pop y push y pcall upage 011 di or #imm or dp or dp+x or !abs ror a ror dp tcall 6 or1 or1b cmpx dp pop psw push psw ret 100 clrv and #imm and dp and dp+x and !abs inc a inc dp tcall 8 and1 and1b cmpy dp cbne dp+x txsp inc x 101 setc eor #imm eor dp eor dp+x eor !abs dec a dec dp tcall 10 eor1 eor1b dbne dp xma dp+x tspx dec x 110 setg lda #imm lda dp lda dp+x lda !abs txa ldy dp tcall 12 ldc ldcb ldx dp ldx dp+y xcn das 111 ei ldm dp,#imm sta dp sta dp+x sta !abs tax sty dp tcall 14 stc m.bit stx dp stx dp+y xax stop low high 10000 10 10001 11 10010 12 10011 13 10100 14 10101 15 10110 16 10111 17 11000 18 11001 19 11010 1a 11011 1b 11100 1c 11101 1d 11110 1e 11111 1f 000 bpl rel clr1 dp.bit bbc a.bit,rel bbc dp.bit,rel adc {x} adc !abs+y adc [dp+x] adc [dp]+y asl !abs asl dp+x tcall 1 jmp !abs bit !abs addw dp ldx #imm jmp [!abs] 001 bvc rel sbc {x} sbc !abs+y sbc [dp+x] sbc [dp]+y rol !abs rol dp+x tcall 3 call !abs test !abs subw dp ldy #imm jmp [dp] 010 bcc rel cmp {x} cmp !abs+y cmp [dp+x] cmp [dp]+y lsr !abs lsr dp+x tcall 5 mul tclr1 !abs cmpw dp cmpx #imm call [dp] 011 bne rel or {x} or !abs+y or [dp+x] or [dp]+y ror !abs ror dp+x tcall 7 dbne y cmpx !abs ldya dp cmpy #imm reti 100 bmi rel and {x} and !abs+y and [dp+x] and [dp]+y inc !abs inc dp+x tcall 9 div cmpy !abs incw dp inc y tay 101 bvs rel eor {x} eor !abs+y eor [dp+x] eor [dp]+y dec !abs dec dp+x tcall 11 xma {x} xma dp decw dp dec y tya 110 bcs rel lda {x} lda !abs+y lda [dp+x] lda [dp]+y ldy !abs ldy dp+x tcall 13 lda {x}+ ldx !abs stya dp xay daa 111 beq rel sta {x} sta !abs+y sta [dp+x] sta [dp]+y sty !abs sty dp+x tcall 15 sta {x}+ stx !abs cbne dp xyx nop
gms800 series june. 2001 v b.3 instruction set arithmetic / logic operation no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 adc #imm 04 2 2 add with carry. 2 adc dp 05 2 3 a ? ( a ) + ( m ) + c 3 adc dp + x 06 2 4 4 adc !abs 07 3 4 nv--h-zc 5 adc !abs + y 15 3 5 6 adc [ dp + x ] 16 2 6 7 adc [ dp ] + y 17 2 6 8 adc { x } 14 1 3 9 and #imm 84 2 2 logical and 10 and dp 85 2 3 a ? ( a ) ( m ) 11 and dp + x 86 2 4 12 and !abs 87 3 4 n-----z- 13 and !abs + y 95 3 5 14 and [ dp + x ] 96 2 6 15 and [ dp ] + y 97 2 6 16 and { x } 94 1 3 17 asl a 08 1 2 arithmetic shift left 18 asl dp 09 2 4 n-----zc 19 asl dp + x 19 2 5 20 asl !abs 18 3 5 21 cmp #imm 44 2 2 compare accumulator contents with memory contents ( a ) - ( m ) 22 cmp dp 45 2 3 23 cmp dp + x 46 2 4 24 cmp !abs 47 3 4 n-----zc 25 cmp !abs + y 55 3 5 26 cmp [ dp + x ] 56 2 6 27 cmp [ dp ] + y 57 2 6 28 cmp { x } 54 1 3 29 cmpx #imm 5e 2 2 compare x contents with memory contents 30 cmpx dp 6c 2 3 ( x ) - ( m ) n-----zc 31 cmpx !abs 7c 3 4 32 cmpy #imm 7e 2 2 compare y contents with memory contents 33 cmpy dp 8c 2 3 ( y ) - ( m ) n-----zc 34 cmpy !abs 9c 3 4 35 com dp 2c 2 4 1s complement : ( dp ) ? ~( dp ) n-----z- 36 daa df 1 3 decimal adjust for addition n-----zc 37 das cf 1 3 decimal adjust for subtraction n-----zc 38 dec a a8 1 2 decrement n-----z- 39 dec dp a9 2 4 m ? ( m ) - 1 n-----z- 40 dec dp + x b9 2 5 n-----z- 41 dec !abs b8 3 5 n-----z- 42 dec x af 1 2 n-----z- 43 dec y be 1 2 n-----z- ? ? ? ? ? ? ? ? 76543210 ? 0 ? c
gms800 series vi june. 2001 44 div 9b 1 12 divide : ya / x q: a, r: y nv--h-z- 45 eor #imm a4 2 2 exclusive or 46 eor dp a5 2 3 a ? ( a ) ? ( m ) 47 eor dp + x a6 2 4 48 eor !abs a7 3 4 n-----z- 49 eor !abs + y b5 3 5 50 eor [ dp + x ] b6 2 6 51 eor [ dp ] + y b7 2 6 52 eor { x } b4 1 3 53 inc a 88 1 2 increment n-----zc 54 inc dp 89 2 4 m ? ( m ) + 1 n-----z- 55 inc dp + x 99 2 5 n-----z- 56 inc !abs 98 3 5 n-----z- 57 inc x 8f 1 2 n-----z- 58 inc y 9e 1 2 n-----z- 59 lsr a 48 1 2 logical shift right 60 lsr dp 49 2 4 n-----zc 61 lsr dp + x 59 2 5 62 lsr !abs 58 3 5 63 mul 5b 1 9 multiply : ya ? y a n-----z- 64 or #imm 64 2 2 logical or 65 or dp 65 2 3 a ? ( a ) ( m ) 66 or dp + x 66 2 4 67 or !abs 67 3 4 n-----z- 68 or !abs + y 75 3 5 69 or [ dp + x ] 76 2 6 70 or [ dp ] + y 77 2 6 71 or { x } 74 1 3 72 rol a 28 1 2 rotate left through carry 73 rol dp 29 2 4 n-----zc 74 rol dp + x 39 2 5 75 rol !abs 38 3 5 76 ror a 68 1 2 rotate right through carry 77 ror dp 69 2 4 n-----zc 78 ror dp + x 79 2 5 79 ror !abs 78 3 5 80 sbc #imm 24 2 2 subtract with carry 81 sbc dp 25 2 3 a ? ( a ) - ( m ) - ~( c ) 82 sbc dp + x 26 2 4 83 sbc !abs 27 3 4 nv--hzc 84 sbc !abs + y 35 3 5 85 sbc [ dp + x ] 36 2 6 86 sbc [ dp ] + y 37 2 6 87 sbc { x } 34 1 3 88 tst dp 4c 2 3 test memory contents for negative or zero, ( dp ) - 00 h n-----z- 89 xcn ce 1 5 exchange nibbles within the accumulator a 7 ~a 4 ? a 3 ~a 0 n-----z- no. mnemonic op code byte no cycle no operation flag nvgbhizc ? ? ? ? ? ? ? ? 76543210 0 ? ? c ? ? ? ? ? ? ? ? 76543210 c ? ? ? ? ? ? ? ? 76543210 c
gms800 series june. 2001 vii register / memory operation no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 lda #imm c4 2 2 load accumulator 2 lda dp c5 2 3 a ? ( m ) 3 lda dp + x c6 2 4 4 lda !abs c7 3 4 5 lda !abs + y d5 3 5 n-----z- 6 lda [ dp + x ] d6 2 6 7 lda [ dp ] + y d7 2 6 8 lda { x } d4 1 3 9 lda { x }+ db 1 4 x- register auto-increment : a ? ( m ) , x ? x + 1 10 ldm dp,#imm e4 3 5 load memory with immediate data : ( m ) ? imm -------- 11 ldx #imm 1e 2 2 load x-register 12 ldx dp cc 2 3 x ? ( m ) n-----z- 13 ldx dp + y cd 2 4 14 ldx !abs dc 3 4 15 ldy #imm 3e 2 2 load y-register 16 ldy dp c9 2 3 y ? ( m ) n-----z- 17 ldy dp + x d9 2 4 18 ldy !abs d8 3 4 19 sta dp e5 2 4 store accumulator contents in memory 20 sta dp + x e6 2 5 ( m ) ? a 21 sta !abs e7 3 5 22 sta !abs + y f5 3 6 -------- 23 sta [ dp + x ] f6 2 7 24 sta [ dp ] + y f7 2 7 25 sta { x } f4 1 4 26 sta { x }+ fb 1 4 x- register auto-increment : ( m ) ? a, x ? x + 1 27 stx dp ec 2 4 store x-register contents in memory 28 stx dp + y ed 2 5 ( m ) ? x -------- 29 stx !abs fc 3 5 30 sty dp e9 2 4 store y-register contents in memory 31 sty dp + x f9 2 5 ( m ) ? y -------- 32 sty !abs f8 3 5 33 tax e8 1 2 transfer accumulator contents to x-register : x ? a n-----z- 34 tay 9f 1 2 transfer accumulator contents to y-register : y ? a n-----z- 35 tspx ae 1 2 transfer stack-pointer contents to x-register : x ? sp n-----z- 36 txa c8 1 2 transfer x-register contents to accumulator: a ? x n-----z- 37 txsp 8e 1 2 transfer x-register contents to stack-pointer: sp ? x n-----z- 38 tya bf 1 2 transfer y-register contents to accumulator: a ? y n-----z- 39 xax ee 1 4 exchange x-register contents with accumulator :x ? a -------- 40 xay de 1 4 exchange y-register contents with accumulator :y ? a -------- 41 xma dp bc 2 5 exchange memory contents with accumulator 42 xma dp+x ad 2 6 ( m ) ? a n-----z- 43 xma {x} bb 1 5 44 xyx fe 1 4 exchange x-register contents with y-register : x ? y --------
gms800 series viii june. 2001 16-bit operation bit manipulation no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 addw dp 1d 2 5 16-bits add without carry ya ? ( ya ) + ( dp +1 ) ( dp ) nv--h-zc 2cmpw dp 5d 2 4 compare ya contents with memory pair contents : (ya) - (dp+1)(dp) n-----zc 3decw dp bd 2 6 decrement memory pair ( dp+1)( dp) ? ( dp+1) ( dp) - 1 n-----z- 4 incw dp 9d 2 6 increment memory pair ( dp+1) ( dp) ? ( dp+1) ( dp ) + 1 n-----z- 5 ldya dp 7d 2 5 load ya ya ? ( dp +1 ) ( dp ) n-----z- 6 stya dp dd 2 5 store ya ( dp +1 ) ( dp ) ? ya -------- 7 subw dp 3d 2 5 16-bits subtract without carry ya ? ( ya ) - ( dp +1) ( dp) nv--h-zc no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 and1 m.bit 8b 3 4 bit and c-flag : c ? ( c ) ( m .bit ) -------c 2 and1b m.bit 8b 3 4 bit and c-flag and not : c ? ( c ) ~( m .bit ) -------c 3 bit dp 0c 2 4 bit test a with memory : mm----z- 4 bit !abs 1c 3 5 z ? ( a ) ( m ) , n ? ( m 7 ) , v ? ( m 6 ) 5 clr1 dp.bit y1 2 4 clear bit : ( m.bit ) ? 0 -------- 6 clra1 a.bit 2b 2 2 clear a bit : ( a.bit ) ? 0 -------- 7 clrc 20 1 2 clear c-flag : c ? 0 -------0 8 clrg 40 1 2 clear g-flag : g ? 0 --0----- 9 clrv 80 1 2 clear v-flag : v ? 0 -0--0--- 10 eor1 m.bit ab 3 5 bit exclusive-or c-flag : c ? ( c ) ? ( m .bit ) -------c 11 eor1b m.bit ab 3 5 bit exclusive-or c-flag and not : c ? ( c ) ? ~(m .bit) -------c 12 ldc m.bit cb 3 4 load c-flag : c ? ( m .bit ) -------c 13 ldcb m.bit cb 3 4 load c-flag with not : c ? ~( m .bit ) -------c 14 not1 m.bit 4b 3 5 bit complement : ( m .bit ) ? ~( m .bit ) -------- 15 or1 m.bit 6b 3 5 bit or c-flag : c ? ( c ) ( m .bit ) -------c 16 or1b m.bit 6b 3 5 bit or c-flag and not : c ? ( c ) ~( m .bit ) -------c 17 set1 dp.bit x1 2 4 set bit : ( m.bit ) ? 1 -------- 18 seta1 a.bit 0b 2 2 set a bit : ( a.bit ) ? 1 -------- 19 setc a0 1 2 set c-flag : c ? 1 -------1 20 setg c0 1 2 set g-flag : g ? 1 --1----- 21 stc m.bit eb 3 6 store c-flag : ( m .bit ) ? c -------- 22 tclr1 !abs 5c 3 6 test and clear bits with a : a - ( m ) , ( m ) ? ( m ) ~( a ) n-----z- 23 tset1 !abs 3c 3 6 test and set bits with a : a - ( m ) , ( m ) ? ( m ) ( a ) n-----z-
gms800 series june. 2001 ix branch / jump operation no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 bbc a.bit,rel y2 2 4/6 branch if bit clear : -------- 2 bbc dp.bit,rel y3 3 5/7 if ( bit ) = 0 , then pc ? ( pc ) + rel 3 bbs a.bit,rel x2 2 4/6 branch if bit set : -------- 4 bbs dp.bit,rel x3 3 5/7 if ( bit ) = 1 , then pc ? ( pc ) + rel 5 bcc rel 50 2 2/4 branch if carry bit clear if ( c ) = 0 , then pc ? ( pc ) + rel -------- 6 bcs rel d0 2 2/4 branch if carry bit set if ( c ) = 1 , then pc ? ( pc ) + rel -------- 7 beq rel f0 2 2/4 branch if equal if ( z ) = 1 , then pc ? ( pc ) + rel -------- 8 bmi rel 90 2 2/4 branch if minus if ( n ) = 1 , then pc ? ( pc ) + rel -------- 9 bne rel 70 2 2/4 branch if not equal if ( z ) = 0 , then pc ? ( pc ) + rel -------- 10 bpl rel 10 2 2/4 branch if minus if ( n ) = 0 , then pc ? ( pc ) + rel -------- 11 bra rel 2f 2 4 branch always pc ? ( pc ) + rel -------- 12 bvc rel 30 2 2/4 branch if overflow bit clear if (v) = 0 , then pc ? ( pc) + rel -------- 13 bvs rel b0 2 2/4 branch if overflow bit set if (v) = 1 , then pc ? ( pc ) + rel -------- 14 call !abs 3b 3 8 subroutine call 15 call [dp] 5f 2 8 m( sp) ? ( pc h ), sp ? sp - 1, m(sp) ? (pc l ), sp ? sp - 1, if !abs, pc ? abs ; if [dp], pc l ? ( dp ), pc h ? ( dp+1 ) . -------- 16 cbne dp,rel fd 3 5/7 compare and branch if not equal : -------- 17 cbne dp+x,rel 8d 3 6/8 if ( a ) 1 ( m ) , then pc ? ( pc ) + rel. 18 dbne dp,rel ac 3 5/7 decrement and branch if not equal : -------- 19 dbne y,rel 7b 2 4/6 if ( m ) 1 0 , then pc ? ( pc ) + rel. 20 jmp !abs 1b 3 3 unconditional jump 21 jmp [!abs] 1f 3 5 pc ? jump address -------- 22 jmp [dp] 3f 2 4 23 pcall upage 4f 2 6 u-page call m(sp) ? ( pc h ), sp ? sp - 1, m(sp) ? ( pc l ), sp ? sp - 1, pc l ? ( upage ), pc h ? 0ff h . -------- 24 tcall n na 1 8 table call : (sp) ? ( pc h ), sp ? sp - 1, m(sp) ? ( pc l ),sp ? sp - 1, pc l ? (table vector l), pc h ? (table vector h) --------
gms800 series x june. 2001 control operation & etc. no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 brk 0f 1 8 software interrupt : b ? 1, m(sp) ? (pc h ), sp ? sp-1, m(s) ? (pc l ), sp ? sp - 1, m(sp) ? (psw), sp ? sp -1, pc l ? ( 0ffde h ) , pc h ? ( 0ffdf h ) . ---1-0-- 2 di 60 1 3 disable all interrupts : i ? 0 -----0-- 3 ei e0 1 3 enable all interrupt : i ? 1 -----1-- 4 nop ff 1 2 no operation -------- 5 pop a 0d 1 4 sp ? sp + 1, a ? m( sp ) 6 pop x 2d 1 4 sp ? sp + 1, x ? m( sp ) -------- 7 pop y 4d 1 4 sp ? sp + 1, y ? m( sp ) 8 pop psw 6d 1 4 sp ? sp + 1, psw ? m( sp ) restored 9 push a 0e 1 4 m( sp ) ? a , sp ? sp - 1 10 push x 2e 1 4 m( sp ) ? x , sp ? sp - 1 -------- 11 push y 4e 1 4 m( sp ) ? y , sp ? sp - 1 12 push psw 6e 1 4 m( sp ) ? psw , sp ? sp - 1 13 ret 6f 1 5 return from subroutine sp ? sp +1, pc l ? m( sp ), sp ? sp +1, pc h ? m( sp ) -------- 14 reti 7f 1 6 return from interrupt sp ? sp +1, psw ? m( sp ), sp ? sp + 1, pc l ? m( sp ), sp ? sp + 1, pc h ? m( sp ) restored 15 stop ef 1 3 stop mode ( halt cpu, stop oscillator ) --------
c. mask order sheet mask order & verification sheet gms81c21xx-hj 1. customer information company name application order date yyyy tel: fax: name & signature: .o tp file file name (please check mark ? into ) customer should write inside thick line box. 40pdip 42sdip 44mqfp ( ) .otp yyww korea gms81c21xx-hj customers logo chollian internet hitel package 12k 20k rom size (bytes) mask data check sum ( ) 2. device information mm dd 3000 h (20k) 5000 h (12k) 7fff h 3. marking specification customer logo is not required. yyww korea gms81c21xx-hj customers part number if the customer logo must be used in the special mark, please submit a clean original of the logo. 4. delivery schedule date quantity hynix confirmation yyyy mm dd yyyy mm dd customer sample risk order pcs pcs e-mail address: 5. rom code verification yyyy mm dd verification date: please confirm out verification data. check sum: tel: fax: name & signature: e-mail address: yyyy mm dd approval date: i agree with your verification data and confirm you to make mask set. tel: fax: name & signature: e-mail address: 12 or 20 set 00 h in blanked area
gms81c21xx mask option list 2. config option check customer should write inside thick line box. 3. h/v port option check (pull-down option check ) 4. normal port option check ( pull-up option check ) ra without pull-down resistor 1. ra/vdisp vdisp 76543210 rco initial value: --00 -0-0 b address: 703f h config lock code protect 0 : allow code read out 1 : lock code read out pfd level selection 00: pfd = 2.7v 01: pfd = 2.7v external rc osc selection 0: crystal or resonator oscillator 1: external rc oscillator pfs0 pfs1 10: pfd = 3.0v 11: pfd = 2.4v port option on off r60/an0 r61/an1 r62/an2 r63/an3 r64/an4 r65/an5 r66/an6 r67/an7 xxx config default value : xx00x0x0 port option on off r53/sclk r54/sin r55/sout r56/pwm r57 port option on off r00/int0 r01/int1 r02/ec0 r03/buzo r04 r05 r06 r07 port option on off r20 r21 r22 r23 r24 r25 r26 r27 port option on off r30 r31 r32 r33 r34 on : with pull-down resistor off : without pull-down resistor on : with pull-up resistor off : without pull-up resistor (please check mark ? into ) x

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